Features; Figure 7.1 Block Diagram Of Dtc - Renesas H8S Series Hardware Manual

Section 7 Data Transfer Controller (DTC)
7.1

Features

•
Transfer is possible over any number of channels
•
Three transfer modes
Normal, repeat, and block transfer modes are available
•
One activation source can trigger a number of data transfers (chain transfer)
•
Direct specification of 16 Mbytes address space is possible
•
Activation by software is possible
•
Transfer can be set in byte or word units
•
A CPU interrupt can be requested for the interrupt that activated the DTC
Interrupt controller
Interrupt
request
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERE:
DTVECR:
Rev. 3.00 Jul. 14, 2005 Page 136 of 986
REJ09B0098-0300
DTC
DTC mode register A, B
DTC transfer count register A, B
DTC source address register
DTC destination address register
DTC enable registers A to E
DTC vector register

Figure 7.1 Block Diagram of DTC

Internal address bus
Internal data bus
On-chip RAM