Renesas H8S Series Hardware Manual page 12

2.7.7 Program-Counter Relative-@(d:8, PC) or @(d:16, PC) ...................................... 50
2.7.8 Memory Indirect-@@aa:8 ................................................................................... 51
2.7.9 Effective Address Calculation ................................................................................ 52
2.8 Processing States.................................................................................................................. 54
2.9 Usage Notes ......................................................................................................................... 56
2.9.1 Note on TAS Instruction Usage.............................................................................. 56
2.9.2 Note on STM/LDM Instruction Usage ................................................................... 56
2.9.3 Note on Bit Manipulation Instructions ................................................................... 56
2.9.4 EEPMOV Instruction.............................................................................................. 57
Section 3 MCU Operating Modes ....................................................................... 59
3.1 Operating Mode Selection ................................................................................................... 59
3.2 Register Descriptions........................................................................................................... 60
3.2.1 Mode Control Register (MDCR) ............................................................................ 60
3.2.2 System Control Register (SYSCR)......................................................................... 61
3.2.3 Serial Timer Control Register (STCR) ................................................................... 63
3.2.4 System Control Register 3 (SYSCR3) .................................................................... 66
3.3 Operating Mode Descriptions .............................................................................................. 67
3.3.1 Mode 2.................................................................................................................... 67
3.3.2 Mode 3.................................................................................................................... 67
3.4 Address Map ........................................................................................................................ 67
Section 4 Exception Handling ............................................................................. 69
4.1 Exception Handling Types and Priority............................................................................... 69
4.2 Exception Sources and Exception Vector Table .................................................................. 70
4.3 Reset .................................................................................................................................... 74
4.3.1 Reset Exception Handling ...................................................................................... 74
4.3.2 Interrupts Immediately after Reset.......................................................................... 75
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 75
4.4 Interrupt Exception Handling .............................................................................................. 76
4.5 Trap Instruction Exception Handling................................................................................... 76
4.6 Stack Status after Exception Handling................................................................................. 77
4.7 Usage Note........................................................................................................................... 78
Section 5 Interrupt Controller.............................................................................. 79
5.1 Features................................................................................................................................ 79
5.2 Input/Output Pins................................................................................................................. 81
5.3 Register Descriptions........................................................................................................... 82
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 83
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 85
Rev. 3.00 Jul. 14, 2005 Page xii of xlviii