Pwm Register Select (Pwsl) - Renesas H8S Series Hardware Manual

Section 9 8-Bit PWM Timer (PWM)
9.3.1

PWM Register Select (PWSL)

PWSL is used to select the input clock and the PWM data register.
Bit Bit Name Initial Value
7 PWCKE 0
6 PWCKS 0
5 — 1
4 — 0
3 RS3 0
2 RS2 0
1 RS1 0
0 RS0 0
[Legend]
x: Don't care.
Rev. 3.00 Jul. 14, 2005 Page 250 of 986
REJ09B0098-0300
R/W Description
R/W PWM Clock Enable
R/W PWM Clock Select
These bits, together with bits PWCKB and PWCKA in
PCSR, select the internal clock input to TCNT in the
PWM. For details, see table 9.2.
The resolution, PWM conversion period, and carrier
frequency depend on the selected internal clock, and
can be obtained from the following equations.
Resolution (minimum pulse width) = 1/internal clock
frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
With a 20 MHz system clock (φ), the resolution, PWM
conversion period, and carrier frequency are as shown
in table 9.3.
R Reserved
Always read as 1 and cannot be modified.
R Reserved
Always read as 0 and cannot be modified.
R/W Register Select
R/W These bits select the PWM data register.
R/W 0xxx: No effect on operation
R/W 1000: PWDR8 selected
1001: PWDR9 selected
1010: PWDR10 selected
1011: PWDR11 selected
1100: PWDR12 selected
1101: PWDR13 selected
1110: PWDR14 selected
1111: PWDR15 selected