Contention Between Counter Clearing By Input Capture And Counter Increment - Renesas H8/3067 Series User Manual

Section 10 8-Bit Timers
10.7.5

Contention between Counter Clearing by Input Capture and Counter Increment

If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case.
T T T
1 2 3
φ
Input capture signal
Counter clear signal
TCNT internal clock
TCNT N H'00
TCORB N
X
Figure 10.22 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 4.00 Jan 26, 2006 page 429 of 938
REJ09B0276-0400