Input Sampling And A/D Conversion Time - Renesas H8S Series Hardware Manual

Section 19 A/D Converter
19.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to
D
1, then starts A/D conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 indicates
the A/D conversion time.
As indicated in figure 19.2, the A/D conversion time (t ) includes t and the input sampling
CONV D
time (t ). The length of t varies depending on the timing of write to ADCSR. The total
SPL D
conversion time therefore varies within the ranges indicated in table 19.3.
In scan mode, the values shown in table 19.3 become those for the first conversion time. For the
second and subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and
134 states (fixed) when CKS = 1. Use the conversion time of 134 states only when the system
clock (φ) is 16 MHz or lower.
Rev. 3.00 Jul. 14, 2005 Page 724 of 986
REJ09B0098-0300