Block Transfer Mode; Figure 7.7 Memory Mapping In Block Transfer Mode; Table 7.5 Register Functions In Block Transfer Mode - Renesas H8S Series Hardware Manual

Section 7 Data Transfer Controller (DTC)
7.5.3

Block Transfer Mode

In block transfer mode, one activation source transfers one block of data. Either the transfer source
or the transfer destination is designated as a block area. Table 7.5 lists the register functions in
block transfer mode. The block size can be between 1 and 256. When the transfer of one block
ends, the initial state of the block size counter and the address register that is specified as the block
area is restored. The other address register is then incremented, decremented, or left fixed
according to the register information. From 1 to 65,536 transfers can be specified. Once the
specified number of transfers has been completed, a CPU interrupt is requested.
Table 7.5 Register Functions in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
SAR
or
DAR

Figure 7.7 Memory Mapping in Block Transfer Mode

Rev. 3.00 Jul. 14, 2005 Page 150 of 986
REJ09B0098-0300
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
1st block
•
•
•
Transfer
N th block
Function
Transfer source address
Transfer destination address
Holds block size
Block size counter
Transfer counter
Block area
DAR
or
SAR