Interrupt Control Mode 0; Table 5.8 Operations And Control Signal Functions In Each Interrupt Control Mode - Renesas H8S Series Hardware Manual

Section 5 Interrupt Controller
Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control Mode INTM1
0 0
1
[Legend]
Ο:
Interrupt operation control is performed
IM: Used as an interrupt mask bit
PR: Priority is set
—: Not used
5.6.1

Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests other than NMI and address break are masked by
ICR and the I bit of CCR in the CPU. Figure 5.7 shows a flowchart of the interrupt acceptance
operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other
than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
Rev. 3.00 Jul. 14, 2005 Page 112 of 986
REJ09B0098-0300
Setting
INTM0
Ο
0
Ο
1
Interrupt Acceptance
Control
3-Level Control
I UI ICR
IM — PR
IM IM PR
Default Priority
Determination
Ο
Ο