Table 12.3 Cclr2 To Cclr0 (Channel 0); Table 12.4 Cclr2 To Cclr0 (Channels 1 And 2) - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)

Table 12.3 CCLR2 to CCLR0 (channel 0)

Bit 7
Channel CCLR2
0 0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register. TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture dose not occur.

Table 12.4 CCLR2 to CCLR0 (channels 1 and 2)

Bit 7
Channel Reserved*
1, 2 0
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
Rev. 3.00 Jul. 14, 2005 Page 312 of 986
REJ09B0098-0300
Bit 6 Bit 5
CCLR1 CCLR0
0 0
1
1 0
1
0 0
1
1 0
1
Bit 6 Bit 5
2
CCLR1 CCLR0
0 0
1
1 0
1
Description
TCNT clearing disabled (Initial value)
TCNT cleared by TGRA compare
match/input capture
TCNT cleared by TGRB compare
match/input capture
TCNT cleared by counter clearing for
another channel performing
synchronous/clearing synchronous
1
operation*
TCNT clearing disabled
TCNT cleared by TGRC compare
2
match/input capture*
TCNT cleared by TGRD compare
2
match/input capture*
TCNT cleared by counter clearing for
another channel performing synchronous
clearing/synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare
match/input capture
TCNT cleared by TGRB compare
match/input capture
TCNT cleared by counter clearing for
another channel performing synchronous
clearing/synchronous operation*
1
1