Table 18.9 Fw Memory Cycle (Byte Transfer) - Renesas H8S Series Hardware Manual

Table 18.9 FW Memory Cycle (Byte Transfer)

FW Memory Read Cycle
State
Count Contents
1 Start
2 Device selection
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Address 5
8 Address 6
9 Address 7
10 Size
11 Turnaround (recovery) Host
12 Turnaround
13 Wait*
14 Synchronization
15 Data 1
16 Data 2
17 Turnaround (recovery) Slave
18 Turnaround
Note: * The number of wait states differs depending on the length of the time to turn the bus
control over and the system clock frequency.
The LPC supports byte, word, and longword transfer of the FW memory read and write cycle.
When transferring in words, the LSB is fixed B'0 and when transferring longwords, the lower two
bits are fixed B'00.
Drive Value
Source (3 to 0)
Host 1101
Host ID3 to ID0
Host Bits 27 to 24
Host Bits 23 to 20
Host Bits 19 to 16
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host 0000
1111
None ZZZZ
Slave 0101/0110
Slave 0000
Slave Bits 3 to 0
Slave Bits 7 to 4
1111
None ZZZZ
Section 18 LPC Interface (LPC)
FW Memory Write Cycle
Contents
Start
Device selection
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Size
Data 1
Data 2
Turnaround (recovery) Host
Turnaround
Synchronization
Turnaround (recovery) Slave
Turnaround
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Rev. 3.00 Jul. 14, 2005 Page 691 of 986
Drive Value
Source (3 to 0)
Host 1110
Host ID3 to ID0
Host Bits 27 to 24
Host Bits 23 to 20
Host Bits 19 to 16
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host 0000
Host Bits 3 to 0
Host Bits 7 to 4
1111
None ZZZZ
Slave 0000
1111
None ZZZZ
 
REJ09B0098-0300