Host Interface Control Registers 2 And 3 (Hicr2 And Hicr3) - Renesas H8S Series Hardware Manual

Bit Bit Name Initial Value Slave Host Description
1 LSMIB 0
0 LSCIB 0
18.3.2

Host Interface Control Registers 2 and 3 (HICR2 and HICR3)

HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the
LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby
mode. The states of other bits are decided by the pin states. The pin states can be monitored by the
pin monitoring bits regardless of the LPC interface operating state or the operating state of the
functions that use pin multiplexing.
• HICR2
Bit Bit Name Initial Value Slave Host Description
7 GA20 Undefined
6 LRST 0
R/W

R/W LSMI Output Bit
Controls LSMI output in combination with the LSMIE
bit. For details, refer to description on the LSMIE bit
in HICR0.

R/W LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit. For details, refer to description on the LSCIE bit
in HICR0.
R/W

R GA20 Pin Monitor
R/(W)* 
LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
•
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
•
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 625 of 986
REJ09B0098-0300