Section 18 LPC Interface (LPC)
Slave CPU
Master CPU
ODR1 write
Interrupt initiation
Write 1 to IRQ1E1
SERIRQ IRQ1 output
SERIRQ IRQ1
ODR1 read
source clear
OBF1 = 0?
No
Yes
All bytes
transferred?
No
Hardware operation
Yes
Software operation
Figure 18.17 HIRQ Flowchart (Example of Channel 1)
Rev. 3.00 Jul. 14, 2005 Page 713 of 986
REJ09B0098-0300