Operation Timing; Tcnt Count Timing; Figure 13.4 Count Timing For Internal Clock Input; Figure 13.5 Count Timing For External Clock Input (Both Edges) - Renesas H8S Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.5

Operation Timing

13.5.1

TCNT Count Timing

Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the
TCNT count timing with an external clock source. The pulse width of the external clock signal
must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both
edges. The counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
TCNT input
clock
TCNT
φ
External clock
input pin
TCNT input
clock
TCNT

Figure 13.5 Count Timing for External Clock Input (Both Edges)

Rev. 3.00 Jul. 14, 2005 Page 398 of 986
REJ09B0098-0300
N – 1

Figure 13.4 Count Timing for Internal Clock Input

N – 1
N
N
N + 1
N + 1