Input/Output Pins; Table 22.1 Pin Configuration - Renesas H8S Series Hardware Manual

22.2

Input/Output Pins

Table 22.1 shows the JTAG pin configuration.

Table 22.1 Pin Configuration

Pin Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Abbreviation I/O
ETCK Input
ETMS Input
ETDI Input
ETDO Output
ETRST
Input
Section 22 Boundary Scan (JTAG)
Function
Test clock input
Provides an independent clock supply to the
JTAG. As the clock input to the ETCK pin is
supplied directly to the JTAG, a clock waveform
with a duty cycle close to 50% should be input.
For details, see section 26, Electrical
Characteristics. If there is no input, the ETCK pin
is fixed to 1 by an internal pull-up.
Test mode select input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP
controller. If there is no input, the ETMS pin is
fixed to 1 by an internal pull-up.
Serial data input
Performs serial input of instructions and data for
JTAG registers. ETDI is sampled on the rise of
the ETCK pin. If there is no input, the ETDI pin is
fixed to 1 by an internal pull-up.
Serial data output
Performs serial output of instructions and data
from JTAG registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the high-
impedance state.
Test reset input signal
Initializes the JTAG asynchronously. If there is
no input, the ETRST pin is fixed to 1 by an
internal pull-up.
Rev. 3.00 Jul. 14, 2005 Page 829 of 986
REJ09B0098-0300