Bit
Bit Name Initial Value Slave Host Description
1
IRQ12E1 0
0
IRQ1E1
0
R/W
R/W
Host IRQ12 Interrupt Enable 1
Enables or disables an HIRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ12 interrupt request by OBF1 and IRQ12E1
is disabled
[Clearing conditions]
•
Writing 0 to IRQ12E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ12 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
•
Writing 1 after reading IRQ12E1 = 0
R/W
Host IRQ1 Interrupt Enable 1
Enables or disables a host HIRQ1 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ1E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
•
Writing 1 after reading IRQ1E1 = 0
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 643 of 986
REJ09B0098-0300