Lpc Interface Clock Start Request; Lpc/Fw Memory Cycle; Figure 18.7 Clock Start Request Timing - Renesas H8S Series Hardware Manual

In order for a slave to transfer an interrupt request in this case, a request to restart the clock must
first be issued to the host. For details see section 18.4.6, LPC Interface Clock Start Request.
18.4.6

LPC Interface Clock Start Request

A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With
LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the
transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt
request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to
the host. The timing for this operation is shown in figure 18.7.
CLK
CLKRUN
Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a
different protocol, using the PME signal, etc.
18.4.7

LPC/FW Memory Cycle

In LPC/FW memory read or LPC/FW memory write cycles, data is transferred via pins LAD3 to
LAD0 in the following order, in synchronization with the LCLK. The slave can report an error to
the host by sending back a value of B'1010 in the synchronization return cycle of the slave. The
LPC of this LSI however a value of B'0000 (ready), B'0101 (short wait), or B'0110(long wait)
always returns.
If the received address matches an address of the area the host can access (the area selected by the
LPC registers: HBAR1, HBAR2, ASSR, RAMBAR, and RAMASSR), the LPC interface enters
the busy state; it returns to the idle state by a turnaround output by the slave. Register and flag
changes are made at this timing, so in the event of a transfer cycle forced termination (abort),
registers and flags are not changed. An on-chip memory, however, is read after receiving an
1
Pull-up enable
Drive by the slave processor

Figure 18.7 Clock Start Request Timing

Section 18 LPC Interface (LPC)
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Drive by the host processor
Rev. 3.00 Jul. 14, 2005 Page 689 of 986
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