Renesas H8S Series Hardware Manual page 566

2
Section 16 I C Bus Interface (IIC)
Bit Bit Name Initial Value R/W
5 MST 0
4 TRS 0
3 ACKE 0
Rev. 3.00 Jul. 14, 2005 Page 518 of 986
REJ09B0098-0300
Description
R/W [MST clearing conditions]
R/W
1. When 0 is written by software
2. When lost in bus contention in I
mode
[MST setting conditions]
1. When 1 is written by software (for MST clearing
condition 1)
2. When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
1. When 0 is written by software (except for TRS setting
condition 3)
2. When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
3. When lost in bus contention in I
mode
[TRS setting conditions]
1. When 1 is written by software (except for TRS clearing
condition 3)
2. When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
3. When 1 is received as the R/W bit after the first frame
address matching in I
R/W Acknowledge Bit Decision and Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the received acknowledge bit is 1, continuous
transfer is halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
2
C bus format master
2
C bus format master
2
C bus format slave mode