Slave Address Register 2 (Sar2); On-Chip Ram Slave Address Register (Ramar) - Renesas H8S Series Hardware Manual

18.3.26 Slave Address Register 2 (SAR2)

SAR2 selects the upper eight bits of slave start address of the flash memory obtained by
translating the host address in HBAR2. The lower 16 bits are fixed H'0000. The contents of this
register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial
Bit Bit Name Value
7 SA2R23 0
6 SA2R22 0
5 SA2R21 0
4 SA2R20 0
3 SA2R19 0
2 SA2R18 0
1 SA2R17 0
0 SA2R16 0

18.3.27 On-Chip RAM Slave Address Register (RAMAR)

RAMAR selects the slave start address (bits 15 to 8) of the on-chip RAM obtained by translating
the host address. Bits 23 to 16 are fixed H'FF and bits 7 to 0 are fixed H'00. The contents of this
register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial
Bit Bit Name Value
7 RMR15 1
6 RMR14 1
5 RMR13 0
4 RMR12 1
3 RMR11 0
2 RMR10 0
1 RMR9 0
0 RMR8 0
Note: The value must be selected so that the area selected by RBUFAR is not overlapped. In
*
this case, data in the on-chip RAM may be changed.
R/W
Slave Host Description

R/W Slave Address Bits 23 to 16

R/W Select bits 23 to 16 of the flash memory address obtained
by translating the host address. The value H'10 to H'FF

R/W
should not be selected.

R/W

R/W

R/W

R/W

R/W
R/W
Slave Host Description

R/W On-Chip RAM Slave Address Bits 15 to 8

R/W Select bits 15 to 8 of the on-chip RAM address obtained
by translating the host address. Though H'D0 to H'EF can

R/W
be set, setting only H'D1 to H'EF is valid. Setting other

R/W
than these values is invalid. When setting is invalid, the

previous value is retained.
R/W

R/W

R/W

R/W
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 671 of 986
REJ09B0098-0300