Receive Abort; Figure 17.6 Transmit Timing - Renesas H8S Series Hardware Manual

I/O inhibit
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
I/O inhibit
KCLK
(output)
KBTE
KTER
KBTS
[4]
[1] to [3]
[5]
17.4.3

Receive Abort

This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard
side) in the event of a protocol error, etc. In this case, the system holds the clock low. During
reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when
the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is
an abort request from the system, and data transmission from the keyboard is aborted. Thus the
system can abort reception by holding the clock low for a certain period. A sample receive abort
processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8.
1 2
Start bit
0
[6] [7] [8]

Figure 17.6 Transmit Timing

Section 17 Keyboard Buffer Control Unit (KBU)
8 9
Parity
1 7
Rev. 3.00 Jul. 14, 2005 Page 597 of 986
10 11
Receive
completed
Stop bit
notification
[9] [10]
REJ09B0098-0300
[11]