Renesas H8S Series Hardware Manual page 569

16-bit single-chip microcomputer
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Bit Bit Name Initial Value R/W
1
IRIC
0
Notes: 1. The value of the BBSY flag is not changed even though it is written to.
2. Only 0 can be written, to clear the flag.
Using DTC clears the IRIC flag automatically and enables consecutive transfer without CPU.
2
When, with the I
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag
which is a DTC activation source is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
2
match in I
C bus format slave mode.
Even if the IRIC and IRTR flags are set, the ICDRE flag or ICDRF flag may not be set. In the case
of continuous transfer by using the DTC, the IRIC and IRTR flags are not cleared after the
specified number of transfers is completed. While, as the specified number of reading/writing
ICDR has been completed, reading/writing of the ICDRE or ICDRF flag is cleared.
Description
2
R/(W) *
Clocked synchronous serial format mode:
At the end of data transfer (rise of the 8th
transmit/receive)
When a start condition is detected
When the ICDRE or ICDRF flag is set to 1 in any
operating mode:
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among the ICDR register
and buffer (when data is transferred from ICDRT to
ICDRS in transmit mode and the ICDRE flag is set to
1, or when data is transferred from ICDRS to ICDRR
in receive mode and the ICDRF flag is set to 1)
[Clearing conditions]
When 0 is written in IRIC after reading IRIC = 1
When ICDR is read/written by the DTC (in some
cases, this condition does not work as clearing
condition, therefore, for details see following
explanation on the operation of DTC)
2
Section 16 I
C Bus Interface (IIC)
Rev. 3.00 Jul. 14, 2005 Page 521 of 986
REJ09B0098-0300

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