Chain Transfer; Figure 7.8 Chain Transfer Operation - Renesas H8S Series Hardware Manual

7.5.4

Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the
register information start address stored at the DTC vector address, and then reads the first register
information at that start address. After the data transfer, the CHNE bit will be tested. When it has
been set to 1, DTC reads the next register information located in a consecutive area and performs
the data transfer. These sequences are repeated until the CHNE bit is cleared to 0.
In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated
at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
DTC vector
address
Register information
start address

Figure 7.8 Chain Transfer Operation

Section 7 Data Transfer Controller (DTC)
Register information
CHNE = 1
Register information
CHNE = 0
Rev. 3.00 Jul. 14, 2005 Page 151 of 986
Source
Destination
Source
Destination
REJ09B0098-0300