Conflict Between Overflow/Underflow And Counter Clearing; Conflict Between Tcnt Write And Overflow/Underflow - Renesas H8SX/1650 Hardware Manual

9.9.11

Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.53 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
P
TCNT input clock
TCNT
Counter clear signal
TGF flag
TCFV flag
Figure 9.53 Conflict between Overflow and Counter Clearing
9.9.12

Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.54 shows the operation timing when there is conflict between TCNT write and overflow.
P
Address
Write
TCNT
TCFV flag
Figure 9.54 Conflict between TCNT Write and Overflow
H'FFFF
Disabled
TGR write cycle
T T
1
TCNT address
H'FFFF
Section 9 16-Bit Timer Pulse Unit (TPU)
H'0000
2
TCNT write data
M
Rev.2.00 Jun. 28, 2007 Page 387 of 666
REJ09B0311-0200