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H8SX/1520 Series
Renesas H8SX/1520 Series Manuals
Manuals and User Guides for Renesas H8SX/1520 Series. We have
3
Renesas H8SX/1520 Series manuals available for free PDF download: Hardware Manual, User Manual
Renesas H8SX/1520 Series Hardware Manual (846 pages)
32-Bit CISC Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.22 MB
Table of Contents
Table of Contents
9
Table of Contents
33
Section 1 Overview
39
Features
39
Block Diagram
40
Figure 1.1 Block Diagram of H8SX/1527
40
Figure 1.2 Block Diagram of H8SX/1525
41
Pin Assignments
42
Figure 1.3 Pin Assignments of H8SX/1527
42
Figure 1.4 Pin Assignments of H8SX/1525
43
Pin Configuration in each Operating Mode
44
Table 1.1 Pin Configuration in each Operating Mode
44
Pin Functions
48
Table 1.2 Pin Functions
48
Section 2 CPU
57
Features
57
Section 2 CPU
58
CPU Operating Modes
59
Normal Mode
59
Figure 2.1 CPU Operating Modes
59
Figure 2.2 Exception Vector Table (Normal Mode)
60
Figure 2.3 Stack Structure (Normal Mode)
60
Middle Mode
61
Advanced Mode
62
Figure 2.4 Exception Vector Table (Middle and Advanced Modes)
62
Maximum Mode
63
Figure 2.5 Stack Structure (Middle and Advanced Modes)
63
Figure 2.6 Exception Vector Table (Maximum Modes)
64
Figure 2.7 Stack Structure (Maximum Mode)
64
Instruction Fetch
65
Address Space
65
Figure 2.8 Memory Map
65
Registers
66
Figure 2.9 CPU Registers
66
General Registers
67
Figure 2.10 Usage of General Registers
67
Program Counter (PC)
68
Condition-Code Register (CCR)
68
Figure 2.11 Stack
68
Extended Control Register (EXR)
70
Vector Base Register (VBR)
70
Short Address Base Register (SBR)
70
Multiply-Accumulate Register (MAC)
71
Initial Values of CPU Registers
71
2Data Formats
71
General Register Data Formats
71
Figure 2.12 General Register Data Formats
72
Memory Data Formats
73
Figure 2.13 Memory Data Formats
73
Instruction Set
74
Table 2.1 Instruction Classification
74
Instructions and Addressing Modes
76
Table 2.2 Combinations of Instructions and Addressing Modes (1)
76
Table 2.2 Combinations of Instructions and Addressing Modes (2)
79
Table of Instructions Classified by Function
80
Table 2.3 Operation Notation
80
Table 2.4 Data Transfer Instructions
81
Table 2.5 Block Transfer Instructions
82
Table 2.6 Arithmetic Operation Instructions
83
Table 2.7 Logic Operation Instructions
85
Table 2.8 Shift Operation Instructions
86
Table 2.9 Bit Manipulation Instructions
87
Table 2.10 Branch Instructions
89
Table 2.11 System Control Instructions
90
Basic Instruction Formats
91
Figure 2.14 Instruction Formats
91
Addressing Modes and Effective Address Calculation
92
Table 2.12 Addressing Modes
92
Register Direct-Rn
93
Register Indirect-@Ern
93
Register Indirect with Displacement-@(D:2, Ern), @(D:16, Ern), or @(D:32, Ern)
93
Index Register Indirect with Displacement-@(D:16,Rnl.b), @(D:32,Rnl.b), @(D:16,Rn.w), @(D:32,Rn.w), @(D:16,Ern.l), or @(D:32,Ern.l)
94
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement-@Ern+, @−Ern, @+Ern, or @Ern
94
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
96
Table 2.13 Absolute Address Access Ranges
96
Immediate-#XX
97
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
97
Program-Counter Relative with Index Register- @(Rnl.b, PC), @(Rn.w, PC), or @(Ern.l, PC)
97
Memory Indirect-@@Aa:8
98
Figure 2.15 Branch Address Specification in Memory Indirect Mode
98
Extended Memory Indirect-@@Vec:7
99
Effective Address Calculation
99
Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
100
MOVA Instruction
101
Table 2.15 Effective Address Calculation for Branch Instructions
101
Processing States
102
Figure 2.16 State Transitions
103
Section 3 MCU Operating Modes
105
Operating Mode Selection
105
Register Descriptions
106
Mode Control Register (MDCR)
106
System Control Register (SYSCR)
107
Table 3.2 Settings of Bits MSD3 to MSD0
107
Operating Mode Descriptions
109
Mode 1
109
Mode 2
109
Mode 3
109
Address Map
110
Address Map (Advanced Mode)
110
Figure 3.1 Address Map (Advanced Mode)
110
Section 4 Exception Handling
111
Exception Handling Types and Priority
111
Table 4.1 Exception Types and Priority
111
Exception Sources and Exception Handling Vector Table
112
Table 4.2 Exception Handling Vector Table
112
Reset
114
Reset Exception Handling
114
Table 4.3 Calculation Method of Exception Handling Vector Table Address
114
Interrupts after Reset
115
On-Chip Peripheral Functions after Reset Release
115
Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)
115
Traces
116
Table 4.4 Status of CCR and EXR after Trace Exception Handling
116
Address Error
117
Address Error Source
117
Table 4.5 Bus Cycle and Address Error
117
Address Error Exception Handling
118
Interrupts
119
Interrupt Sources
119
Table 4.6 States of CCR and EXR after Address Error Exception Handling
119
Table 4.7 Interrupt Sources
119
Interrupt Exception Handling
120
Instruction Exception Handling
121
Trap Instruction
121
Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling
121
Exception Handling by Illegal Instruction
122
Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling
122
Stack Status after Exception Handling
123
Figure 4.2 Stack Status after Exception Handling
123
Usage Note
124
Figure 4.3 Operation When SP Value Is Odd
124
Section 5 Interrupt Controller
125
Features
125
Input/Output Pins
126
Figure 5.1 Block Diagram of Interrupt Controller
126
Table 5.1 Pin Configuration
126
Register Descriptions
127
Interrupt Control Register (INTCR)
127
CPU Priority Control Register (CPUPCR)
128
Interrupt Priority Registers a to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR)
130
IRQ Enable Register (IER)
132
IRQ Sense Control Registers H and L (ISCRH and ISCRL)
134
IRQ Status Register (ISR)
139
Software Standby Release IRQ Enable Register (SSIER)
140
Interrupt Sources
141
External Interrupts
141
Internal Interrupts
142
Figure 5.2 Block Diagram of Interrupts Irqn
142
Interrupt Exception Handling Vector Table
143
Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority
143
Interrupt Control Modes and Interrupt Operation
150
Interrupt Control Mode 0
150
Table 5.3 Interrupt Control Modes
150
Interrupt Control Mode 2
152
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 2
153
Interrupt Exception Handling Sequence
154
Figure 5.5 Interrupt Exception Handling
154
Interrupt Response Times
155
Table 5.4 Interrupt Response Times
155
DMAC Activation by Interrupt
156
Figure 5.6 Block Diagram of DMAC and Interrupt Controller
156
Table 5.5 Number of Execution States in Interrupt Handling Routine
156
Table 5.6 Interrupt Source Selection and Clear Control
157
CPU Priority Control Function over DMAC
158
Table 5.7 CPU Priority Control
159
Table 5.8 Example of Priority Control Function Setting and Control State
159
Usage Notes
160
Conflict between Interrupt Generation and Disabling
160
Figure 5.7 Conflict between Interrupt Generation and Disabling
160
Instructions that Disable Interrupts
161
Times When Interrupts Are Disabled
161
Interrupts During Execution of EEPMOV Instruction
161
Interrupts During Execution of MOVMD and MOVSD Instructions
161
Interrupt Flags of Peripheral Modules
162
Section 6 Bus Controller (BSC)
163
Features
163
Figure 6.1 Block Diagram of Bus Controller
163
Register Descriptions
164
Bus Control Register 2 (BCR2)
164
Bus Configuration
165
Figure 6.2 Internal Bus Configuration
165
Multi-Clock Function
166
Table 6.1 Synchronization Clocks and Their Corresponding Functions
166
Internal Bus
167
Access to Internal Address Space
167
Table 6.2 Number of Access Cycles for On-Chip Memory Spaces
167
Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules
167
Write Data Buffer Function
168
Write Data Buffer Function for Peripheral Module
168
Figure 6.3 Example of Timing When Write Data Buffer Function Is Used
168
Bus Arbitration
169
Operation
169
Bus Transfer Timing
169
Bus Controller Operation in Reset
170
Usage Notes
170
Section 7 DMA Controller (DMAC)
171
Features
171
Figure 7.1 Block Diagram of DMAC
173
Register Descriptions
174
DMA Source Address Register (DSAR)
175
DMA Destination Address Register (DDAR)
176
DMA Offset Register (DOFR)
177
DMA Transfer Count Register (DTCR)
178
DMA Block Size Register (DBSR)
179
DMA Mode Control Register (DMDR)
180
Table 7.1 Data Access Size, Valid Bits, and Settable Size
180
DMA Address Control Register (DACR)
189
Table 7.2 Settings and Areas of Extended Repeat Area
194
DMA Module Request Select Register (DMRSR)
195
Transfer Modes
195
Table 7.3 Transfer Modes
195
Operations
196
Address Modes
196
Figure 7.2 Example of Signal Timing in Dual Address Mode
197
Figure 7.3 Operations in Dual Address Mode
197
Figure 7.4 Data Flow in Single Address Mode
198
Figure 7.5 Example of Signal Timing in Single Address Mode
199
Figure 7.6 Operations in Single Address Mode
199
Transfer Modes
200
Figure 7.7 Example of Signal Timing in Normal Transfer Mode
200
Figure 7.8 Operations in Normal Transfer Mode
200
Figure 7.9 Operations in Repeat Transfer Mode
201
Figure 7.10 Operations in Block Transfer Mode
202
Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified)
203
Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified)
203
Activation Sources
204
Table 7.4 List of On-Chip Module Interrupts to DMAC
205
Bus Access Modes
206
Figure 7.13 Example of Timing in Cycle Stealing Mode
207
Figure 7.14 Example of Timing in Burst Mode
207
Extended Repeat Area Function
208
Figure 7.15 Example of Extended Repeat Area Operation
209
Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode
209
Address Update Function Using Offset
210
Figure 7.17 Address Update Method
210
Figure 7.18 Operation of Offset Addition
211
Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
212
Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
213
Register During DMA Transfer
214
Figure 7.21 Procedure for Changing Register Setting for Channel Being Transferred
217
Priority of Channels
219
Figure 7.22 Example of Timing for Channel Priority
219
Table 7.5 Priority Among DMAC Channels
219
DMA Basic Bus Cycle
220
Figure 7.23 Example of Bus Timing of DMA Transfer
220
Bus Cycles in Dual Address Mode
221
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
221
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment)
222
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement)
222
Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access
223
Figure 7.28 Example of Transfer in Block Transfer Mode
224
Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge
225
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level
226
Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level
227
Figure 7.32 Example of Transfer in Normal Transfer Mode Activated
228
Bus Cycles in Single Address Mode
229
Figure 7.33 Example of Transfer in Single Address Mode (Byte Read)
229
Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)
230
Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge
231
Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level
232
Figure 7.37 Example of Transfer in Single Address Mode Activated
233
DMA Transfer End
234
Relationship Among DMAC and Other Bus Masters
236
CPU Priority Control Function over DMAC
236
Bus Arbitration Among DMAC and Other Bus Masters
237
Interrupt Sources
238
Table 7.6 Interrupt Sources and Priority
238
Figure 7.38 Interrupt and Interrupt Sources
240
Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source
240
Notes on Usage
241
Section 8 I/O Ports
243
Table 8.1 Port Functions
243
Register Descriptions
248
Table 8.2 Register Configuration in each Port
248
Figure 8.1 Port Block Diagram
249
Data Direction Register (Pnddr) (N = 1 to 3, 6, A, D, H, J, and K)
250
Data Register (Pndr) (N = 1 to 3, 6, A, D, H, J, and K)
250
Port Register (Portn) (N = 1 to 6, A, D, H, J, and K)
251
Input Buffer Control Register (Pnicr) (N = 1 to 6, A, D, H, J, and K)
251
Pull-Up MOS Control Register (Pnpcr) (N = D, H, J, and K)
252
Table 8.3 Input Pull-Up MOS State
252
Open-Drain Control Register (Pnodr) (N = 2)
253
Port H Realtime Input Data Register (PHRTIDR)
253
Output Buffer Control
254
Port 1
254
Port 2
257
Port 3
259
Port 6
263
Port a
265
Port D
268
Port H
271
Port J
271
Port K
274
Table 8.4 Available Output Signals and Settings in each Port
277
Port Function Controller
281
Port Function Control Register 9 (PFCR9)
281
Port Function Control Register a (PFCRA)
283
Port Function Control Register B (PFCRB)
285
Usage Notes
287
Notes on Input Buffer Control Register (ICR) Setting
287
Notes on Port Function Control Register (PFCR) Settings
287
Section 9 16-Bit Timer Pulse Unit (TPU)
289
Features
289
Table 9.1 Unit Configuration for each Product
290
Table 9.2 TPU Functions (Unit 0)
290
Table 9.3 TPU Functions (Unit 1)
292
Figure 9.1 Block Diagram of TPU (Unit 0)
294
Figure 9.2 Block Diagram of TPU (Unit 1)
295
Input/Output Pins
296
Table 9.4 Pin Configuration
296
Register Descriptions
298
Timer Control Register (TCR)
303
Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3)
304
Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
304
Table 9.7 Input Clock Edge Selection
305
Table 9.8 TPSC2 to TPSC0 (Channel 0)
305
Table 9.9 TPSC2 to TPSC0 (Channel 1)
305
Table 9.10 TPSC2 to TPSC0 (Channel 2)
306
Table 9.11 TPSC2 to TPSC0 (Channel 3)
306
Table 9.12 TPSC2 to TPSC0 (Channel 4)
307
Table 9.13 TPSC2 to TPSC0 (Channel 5)
307
Timer Mode Register (TMDR)
308
Table 9.14 MD3 to MD0
309
Timer I/O Control Register (TIOR)
310
Table 9.15 TIORH_0
312
Table 9.16 TIORL_0
313
Table 9.17 TIOR_1
314
Table 9.18 TIOR_2
315
Table 9.19 TIORH_3
316
Table 9.20 TIORL_3
317
Table 9.21 TIOR_4
318
Table 9.22 TIOR_5
319
Table 9.23 TIORH_0
320
Table 9.24 TIORL_0
321
Table 9.25 TIOR_1
322
Table 9.26 TIOR_2
323
Table 9.27 TIORH_3
324
Table 9.28 TIORL_3
325
Table 9.29 TIOR_4
326
Table 9.30 TIOR_5
327
Timer Interrupt Enable Register (TIER)
328
Timer Status Register (TSR)
330
Timer Counter (TCNT)
334
Timer General Register (TGR)
334
Timer Start Register (TSTR)
335
Timer Synchronous Register (TSYR)
336
Operation
337
Basic Functions
337
Figure 9.3 Example of Counter Operation Setting Procedure
337
Figure 9.4 Free-Running Counter Operation
338
Figure 9.5 Periodic Counter Operation
339
Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match
339
Figure 9.7 Example of 0-Output/1-Output Operation
340
Figure 9.8 Example of Toggle Output Operation
340
Figure 9.9 Example of Setting Procedure for Input Capture Operation
341
Figure 9.10 Example of Input Capture Operation
342
Synchronous Operation
343
Figure 9.11 Example of Synchronous Operation Setting Procedure
343
Figure 9.12 Example of Synchronous Operation
344
Buffer Operation
345
Figure 9.13 Compare Match Buffer Operation
345
Table 9.31 Register Combinations in Buffer Operation
345
Figure 9.14 Input Capture Buffer Operation
346
Figure 9.15 Example of Buffer Operation Setting Procedure
346
Figure 9.16 Example of Buffer Operation (1)
347
Figure 9.17 Example of Buffer Operation (2)
348
Cascaded Operation
349
Figure 9.18 Example of Cascaded Operation Setting Procedure
349
Table 9.32 Cascaded Combinations
349
Figure 9.19 Example of Cascaded Operation (1)
350
Figure 9.20 Example of Cascaded Operation (2)
350
PWM Modes
351
Table 9.33 PWM Output Registers and Output Pins
352
Figure 9.21 Example of PWM Mode Setting Procedure
353
Figure 9.22 Example of PWM Mode Operation (1)
354
Figure 9.23 Example of PWM Mode Operation (2)
354
Figure 9.24 Example of PWM Mode Operation (3)
355
Phase Counting Mode
356
Table 9.34 Clock Input Pins in Phase Counting Mode
356
Figure 9.25 Example of Phase Counting Mode Setting Procedure
357
Figure 9.26 Example of Phase Counting Mode 1 Operation
358
Table 9.35 Up/Down-Count Conditions in Phase Counting Mode 1
358
Figure 9.27 Example of Phase Counting Mode 2 Operation
359
Table 9.36 Up/Down-Count Conditions in Phase Counting Mode 2
359
Figure 9.28 Example of Phase Counting Mode 3 Operation
360
Table 9.37 Up/Down-Count Conditions in Phase Counting Mode 3
360
Figure 9.29 Example of Phase Counting Mode 4 Operation
361
Table 9.38 Up/Down-Count Conditions in Phase Counting Mode 4
361
Figure 9.30 Phase Counting Mode Application Example
363
Interrupt Sources
364
Table 9.39 TPU Interrupts
364
DMAC Activation
367
A/D Converter Activation
367
Operation Timing
368
Input/Output Timing
368
Figure 9.31 Count Timing in Internal Clock Operation
368
Figure 9.32 Count Timing in External Clock Operation
368
Figure 9.33 Output Compare Output Timing
369
Figure 9.34 Input Capture Input Signal Timing
369
Figure 9.35 Counter Clear Timing (Compare Match)
370
Figure 9.36 Counter Clear Timing (Input Capture)
370
Figure 9.37 Buffer Operation Timing (Compare Match)
371
Figure 9.38 Buffer Operation Timing (Input Capture)
371
Interrupt Signal Timing
372
Figure 9.39 TGI Interrupt Timing (Compare Match)
372
Figure 9.40 TGI Interrupt Timing (Input Capture)
372
Figure 9.41 TCIV Interrupt Setting Timing
373
Figure 9.42 TCIU Interrupt Setting Timing
373
Figure 9.43 Timing for Status Flag Clearing by CPU
374
Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)
374
Usage Notes
375
Module Stop Mode Setting
375
Input Clock Restrictions
375
Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)
375
Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
375
Caution on Cycle Setting
376
Conflict between TCNT Write and Clear Operations
376
Figure 9.47 Conflict between TCNT Write and Clear Operations
376
Conflict between TCNT Write and Increment Operations
377
Conflict between TGR Write and Compare Match
377
Figure 9.48 Conflict between TCNT Write and Increment Operations
377
Figure 9.49 Conflict between TGR Write and Compare Match
377
Conflict between Buffer Register Write and Compare Match
378
Conflict between TGR Read and Input Capture
378
Figure 9.50 Conflict between Buffer Register Write and Compare Match
378
Figure 9.51 Conflict between TGR Read and Input Capture
378
Conflict between TGR Write and Input Capture
379
Conflict between Buffer Register Write and Input Capture
379
Figure 9.52 Conflict between TGR Write and Input Capture
379
Figure 9.53 Conflict between Buffer Register Write and Input Capture
379
Conflict between Overflow/Underflow and Counter Clearing
380
Conflict between TCNT Write and Overflow/Underflow
380
Figure 9.54 Conflict between Overflow and Counter Clearing
380
Figure 9.55 Conflict between TCNT Write and Overflow
380
Multiplexing of I/O Pins
381
Interrupts and Module Stop Mode
381
Section 10 Programmable Pulse Generator (PPG)
383
Features
383
Figure 10.1 Block Diagram of PPG
383
Input/Output Pins
384
Table 10.1 Pin Configuration
384
Register Descriptions
385
Next Data Enable Registers H, L (NDERH, NDERL)
385
Output Data Registers H, L (PODRH, PODRL)
387
Next Data Registers H, L (NDRH, NDRL)
388
PPG Output Control Register (PCR)
391
PPG Output Mode Register (PMR)
392
Operation
394
Output Timing
394
Figure 10.2 Schematic Diagram of PPG
394
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)
394
Sample Setup Procedure for Normal Pulse Output
395
Figure 10.4 Setup Procedure for Normal Pulse Output (Example)
395
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)
396
Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output)
396
Non-Overlapping Pulse Output
397
Figure 10.6 Non-Overlapping Pulse Output
397
Figure 10.7 Non-Overlapping Operation and NDR Write Timing
398
Sample Setup Procedure for Non-Overlapping Pulse Output
399
Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
399
Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)
400
Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary)
400
Inverted Pulse Output
402
Figure 10.10 Inverted Pulse Output (Example)
402
Pulse Output Triggered by Input Capture
403
Usage Notes
403
Module Stop Mode Setting
403
Operation of Pulse Output Pins
403
Figure 10.11 Pulse Output Triggered by Input Capture (Example)
403
Section 11 Watchdog Timer (WDT)
405
Features
405
Figure 11.1 Block Diagram of WDT
405
Register Descriptions
406
Timer Counter (TCNT)
406
Timer Control/Status Register (TCSR)
407
Reset Control/Status Register (RSTCSR)
408
Operation
410
Watchdog Timer Mode
410
Figure 11.2 Operation in Watchdog Timer Mode
410
Interval Timer Mode
411
Interrupt Source
411
Figure 11.3 Operation in Interval Timer Mode
411
Table 11.1 WDT Interrupt Source
411
Usage Notes
412
Notes on Register Access
412
Figure 11.4 Writing to TCNT, TCSR, and RSTCSR
412
Conflict between Timer Counter (TCNT) Write and Increment
413
Changing Values of Bits CKS2 to CKS0
413
Switching between Watchdog Timer Mode and Interval Timer Mode
413
Figure 11.5 Conflict between TCNT Write and Increment
413
Transition to Watchdog Timer Mode or Software Standby Mode
414
Section 12 Serial Communication Interface (SCI)
415
Features
415
Figure 12.1 Block Diagram of SCI
416
Input/Output Pins
417
Table 12.1 Pin Configuration
417
Register Descriptions
418
Receive Shift Register (RSR)
419
Receive Data Register (RDR)
419
Transmit Data Register (TDR)
419
Transmit Shift Register (TSR)
420
Serial Mode Register (SMR)
420
Serial Control Register (SCR)
423
Serial Status Register (SSR)
427
Smart Card Mode Register (SCMR)
435
Bit Rate Register (BRR)
436
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
436
Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
437
Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
438
Table 12.4 Maximum Bit Rate for each Operating Frequency (Asynchronous Mode)
439
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
439
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
440
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
441
Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, N = 0, S = 372)
442
Table 12.9 Maximum Bit Rate for each Operating Frequency (Smart Card Interface Mode, S = 372)
442
Operation in Asynchronous Mode
443
Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
443
Data Transfer Format
444
Table 12.10 Serial Transfer Formats (Asynchronous Mode)
444
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
445
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
445
Clock
446
Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode)
446
SCI Initialization (Asynchronous Mode)
447
Figure 12.5 Sample SCI Initialization Flowchart
447
Serial Data Transmission (Asynchronous Mode)
448
Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
448
Figure 12.7 Sample Serial Transmission Flowchart
449
Serial Data Reception (Asynchronous Mode)
450
Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit)
450
Table 12.11 SSR Status Flags and Receive Data Handling
451
Figure 12.9 Sample Serial Reception Flowchart (1)
452
Figure 12.9 Sample Serial Reception Flowchart (2)
453
Multiprocessor Communication Function
454
Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
455
Multiprocessor Serial Data Transmission
456
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
456
Multiprocessor Serial Data Reception
457
Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
457
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
458
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
459
Operation in Clocked Synchronous Mode
460
Clock
460
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)
460
SCI Initialization (Clocked Synchronous Mode)
461
Figure 12.15 Sample SCI Initialization Flowchart
461
Serial Data Transmission (Clocked Synchronous Mode)
462
Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode
463
Figure 12.17 Sample Serial Transmission Flowchart
463
Serial Data Reception (Clocked Synchronous Mode)
464
Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode
464
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
465
Figure 12.19 Sample Serial Reception Flowchart
465
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
466
Operation in Smart Card Interface Mode
467
Sample Connection
467
Figure 12.21 Pin Connection for Smart Card Interface
467
Data Format (Except in Block Transfer Mode)
468
Figure 12.22 Data Formats in Normal Smart Card Interface Mode
468
Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0)
468
Block Transfer Mode
469
Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)
469
Receive Data Sampling Timing and Reception Margin
470
Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate)
470
Initialization
471
Data Transmission (Except in Block Transfer Mode)
472
Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode
473
Figure 12.27 TEND Flag Set Timing During Transmission
473
Figure 12.28 Sample Transmission Flowchart
474
Serial Data Reception (Except in Block Transfer Mode)
475
Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode
475
Clock Output Control
476
Figure 12.30 Sample Reception Flowchart
476
Figure 12.31 Clock Output Fixing Timing
476
Figure 12.32 Clock Stop and Restart Procedure
477
Interrupt Sources
478
Interrupts in Normal Serial Communication Interface Mode
478
Table 12.12 SCI Interrupt Sources
478
Interrupts in Smart Card Interface Mode
479
Table 12.13 SCI Interrupt Sources
479
Usage Notes
480
Module Stop Mode Setting
480
Break Detection and Processing
480
Mark State and Break Detection
480
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
480
Relation between Writing to TDR and TDRE Flag
481
Restrictions on Using DMAC
481
Figure 12.33 Sample Transmission Using DMAC in Clocked Synchronous Mode
481
SCI Operations During Mode Transitions
482
Figure 12.34 Sample Flowchart for Mode Transition During Transmission
483
Figure 12.35 Port Pin States During Mode Transition (Internal Clock, Asynchronous Transmission)
484
Figure 12.36 Port Pin States During Mode Transition (Internal Clock, Clocked Synchronous Transmission)
484
Figure 12.37 Sample Flowchart for Mode Transition During Reception
485
Section 13 Controller Area Network (HCAN)
487
Features
487
Figure 13.1 HCAN Block Diagram
488
Input/Output Pins
489
Table 13.1 Pin Configuration
489
Register Descriptions
490
Master Control Register (MCR)
491
General Status Register (GSR)
492
Bit Configuration Register (BCR)
494
Mailbox Configuration Register (MBCR)
496
Transmit Wait Register (TXPR)
497
Transmit Wait Cancel Register (TXCR)
498
Transmit Acknowledge Register (TXACK)
499
Abort Acknowledge Register (ABACK)
500
Receive Complete Register (RXPR)
501
Remote Request Register (RFPR)
502
Interrupt Register (IRR)
503
Mailbox Interrupt Mask Register (MBIMR)
508
Interrupt Mask Register (IMR)
509
Receive Error Counter (REC)
511
Transmit Error Counter (TEC)
511
Unread Message Status Register (UMSR)
512
Local Acceptance Filter Masks (LAFML, LAFMH)
513
Message Control (MC0 to MC15)
516
Figure 13.2 Message Control Register Configuration
516
Figure 13.3 Standard Format
516
Figure 13.4 Extended Format
516
Message Data (MD0 to MD15)
519
Figure 13.5 Message Data Configuration
519
HCAN Monitor Register (HCANMON)
521
Operation
522
Hardware and Software Resets
522
Initialization after Hardware Reset
522
Figure 13.6 Hardware Reset Flowchart
523
Figure 13.7 Software Reset Flowchart
524
Figure 13.8 Detailed Description of One Bit
525
Table 13.2 Limits for the Settable Value
525
Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR
526
Message Transmission
528
Figure 13.9 Transmission Flowchart
528
Figure 13.10 Transmit Message Cancellation Flowchart
531
Message Reception
532
Figure 13.11 Reception Flowchart
532
Figure 13.12 Unread Message Overwrite Flowchart
535
HCAN Sleep Mode
536
Figure 13.13 HCAN Sleep Mode Flowchart
536
HCAN Halt Mode
538
Figure 13.14 HCAN Halt Mode Flowchart
538
Interrupt Sources
539
Table 13.4 HCAN Interrupt Sources
539
DMAC Interface
540
Figure 13.15 DMAC Transfer Flowchart
540
CAN Bus Interface
541
Figure 13.16 High-Speed Interface Using PCA82C250
541
Usage Notes
542
Module Stop Mode Setting
542
Reset
542
HCAN Sleep Mode
542
Interrupts
543
Error Counters
543
Register Access
543
Register Hold in Standby Modes
543
Use on Bit Manipulation Instructions
543
HCAN TXCR Operation
544
13.8.10 HCAN Transmission Setting
545
13.8.11 Canceling HCAN Reset and HCAN Sleep Mode
545
13.8.12 Accessing Mailbox in HCAN Sleep Mode
545
Table 13.5 Duration between Transmission Setting
545
Section 14 Synchronous Serial Communication Unit (SSU)
547
Features
547
Figure 14.1 Block Diagram of SSU
548
Input/Output Pins
549
Table 14.1 Pin Configuration
549
Register Descriptions
550
SS Control Register H (SSCRH)
552
SS Control Register L (SSCRL)
554
SS Mode Register (SSMR)
555
SS Enable Register (SSER)
556
SS Status Register (SSSR)
557
SS Control Register 2 (SSCR2)
559
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
561
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
562
Table 14.2 Correspondence between DATS Bit Setting and SSTDR
562
SS Shift Register (SSTRSR)
563
Table 14.3 Correspondence between DATS Bit Setting and SSRDR
563
Operation
564
Transfer Clock
564
Relationship of Clock Phase, Polarity, and Data
564
Figure 14.2 Relationship of Clock Phase, Polarity, and Data
564
Relationship between Data Input/Output Pins and Shift Register
565
Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register
565
Communication Modes and Pin Functions
566
Table 14.4 Communication Modes and Pin States of SSI and SSO Pins
566
Table 14.5 Communication Modes and Pin States of SSCK Pin
567
Table 14.6 Communication Modes and Pin States of SCS Pin
567
SSU Mode
568
Figure 14.4 Example of Initial Settings in SSU Mode
568
Figure 14.5 Example of Transmission Operation (SSU Mode)
570
Figure 14.6 Flowchart Example of Data Transmission (SSU Mode)
571
Figure 14.7 Example of Reception Operation (SSU Mode)
573
Figure 14.8 Flowchart Example of Data Reception (SSU Mode)
574
Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
575
SCS Pin Control and Conflict Error
576
Figure 14.10 Conflict Error Detection Timing (before Transfer)
576
Figure 14.11 Conflict Error Detection Timing (after Transfer End)
576
Clock Synchronous Communication Mode
577
Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode
577
Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode)
578
Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)
579
Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode)
580
Figure 14.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode)
581
Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)
582
Interrupt Requests
583
Table 14.7 Interrupt Sources
583
Usage Note
584
Setting of Module Stop Mode
584
Notes on Clearing Module Stop Mode
584
Section 15 A/D Converter
585
Features
585
Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)
587
Input/Output Pins
588
Table 15.1 Pin Configuration
588
Register Descriptions
589
A/D Data Registers a to H (ADDRA to ADDRH)
590
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
590
A/D Control/Status Register (ADCSR)
591
A/D Control Register (ADCR)
593
Operation
594
Single Mode
594
Scan Mode
595
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
595
Figure 15.4 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected)
596
Input Sampling and A/D Conversion Time
597
Figure 15.5 A/D Conversion Timing
597
External Trigger Input Timing
598
Figure 15.6 External Trigger Input Timing
598
Table 15.3 A/D Conversion Characteristics (Single Mode)
598
Table 15.4 A/D Conversion Characteristics (Scan Mode)
598
Interrupt Source
599
A/D Conversion Accuracy Definitions
599
Table 15.5 A/D Converter Interrupt Source
599
Figure 15.7 A/D Conversion Accuracy Definitions
600
Figure 15.8 A/D Conversion Accuracy Definitions
600
Usage Notes
601
Module Stop Mode Setting
601
Permissible Signal Source Impedance
601
Figure 15.9 Example of Analog Input Circuit
601
Influences on Absolute Accuracy
602
Setting Range of Analog Power Supply and Other Pins
602
Notes on Board Design
602
Notes on Noise Countermeasures
603
Figure 15.10 Example of Analog Input Protection Circuit
603
Table 15.6 Analog Pin Specifications
603
A/D Input Hold Function in Software Standby Mode
604
Figure 15.11 Analog Input Pin Equivalent Circuit
604
Section 16 RAM
605
Section 17 Flash Memory (0.18-ΜM F-ZTAT Version)
607
Features
607
Figure 17.1 Block Diagram of Flash Memory
608
Mode Transition Diagram
609
Figure 17.2 Mode Transition of Flash Memory
609
Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode
610
Memory MAT Configuration
611
Figure 17.3 Memory MAT Configuration
611
Block Structure
612
Figure 17.4 Block Structure of User MAT
612
Programming/Erasing Interface
613
Figure 17.5 Procedure for Creating Procedure Program
613
Input/Output Pins
615
Table 17.2 Pin Configuration
615
Register Descriptions
616
Programming/Erasing Interface Registers
617
Table 17.3 Registers/Parameters and Target Modes
617
Programming/Erasing Interface Parameters
624
Table 17.4 Parameters and Target Modes
624
RAM Emulation Register (RAMER)
636
On-Board Programming Mode
637
Boot Mode
637
Figure 17.6 System Configuration in Boot Mode
637
Table 17.5 On-Board Programming Mode Setting
637
Figure 17.7 Automatic-Bit-Rate Adjustment Operation
638
Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
638
Figure 17.8 Boot Mode State Transition Diagram
639
User Program Mode
641
Figure 17.9 Programming/Erasing Flow
641
Figure 17.10 RAM Map When Programming/Erasing Is Executed
642
Figure 17.11 Programming Procedure in User Program Mode
643
Figure 17.12 Erasing Procedure in User Program Mode
648
Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode
650
User Boot Mode
651
Figure 17.14 Procedure for Programming User MAT in User Boot Mode
652
Figure 17.15 Procedure for Erasing User MAT in User Boot Mode
654
On-Chip Program and Storable Area for Program Data
655
Table 17.7 Executable Memory MAT
656
Table 17.8 Usable Area for Programming in User Program Mode
657
Table 17.9 Usable Area for Erasure in User Program Mode
658
Table 17.10 Usable Area for Programming in User Boot Mode
659
Table 17.11 Usable Area for Erasure in User Boot Mode
660
Protection
661
Hardware Protection
661
Table 17.12 Hardware Protection
661
Software Protection
662
Error Protection
662
Table 17.13 Software Protection
662
Figure 17.16 Transitions to Error Protection State
663
Flash Memory Emulation Using RAM
664
Figure 17.17 RAM Emulation Flow
664
Figure 17.18 Address Map of Overlaid RAM Area
665
Figure 17.19 Programming Tuned Data
666
Switching between User MAT and User Boot MAT
667
Figure 17.20 Switching between User MAT and User Boot MAT
667
Programmer Mode
668
Standard Serial Communication Interface Specifications for Boot Mode
668
Table 17.14 Device Types Supported in Programmer Mode
668
Figure 17.21 Boot Program States
669
Figure 17.22 Bit-Rate-Adjustment Sequence
670
Figure 17.23 Communication Protocol Format
671
Table 17.15 Inquiry and Selection Commands
672
Figure 17.24 New Bit-Rate Selection Sequence
682
Table 17.16 Programming/Erasing Commands
685
Figure 17.25 Programming Sequence
686
Figure 17.26 Erasure Sequence
687
Table 17.17 Status Code
695
Table 17.18 Error Code
695
Usage Notes
696
Section 18 Clock Pulse Generator
699
Figure 18.1 Block Diagram of Clock Pulse Generator
699
Register Description
700
System Clock Control Register (SCKCR)
700
Oscillator
703
Connecting Crystal Resonator
703
Figure 18.2 Connection of Crystal Resonator (Example)
703
Figure 18.3 Crystal Resonator Equivalent Circuit
703
Table 18.1 Damping Resistance Value
703
External Clock Input
704
PLL Circuit
704
Frequency Divider
704
Figure 18.4 External Clock Input (Examples)
704
Table 18.2 Crystal Resonator Characteristics
704
Usage Notes
705
Notes on Clock Pulse Generator
705
Figure 18.5 Clock Modification Timing
705
Notes on Resonator
706
Notes on Board Design
706
Figure 18.6 Note on Board Design for Oscillation Circuit
706
Notes on Input Clock Frequency
707
Figure 18.7 Connection Example of Bypass Capacitor
707
Section 19 Power-Down Modes
709
Features
709
Table 19.1 Operating States
709
Register Descriptions
710
Figure 19.1 Mode Transitions
710
Standby Control Register (SBYCR)
711
Module Stop Control Registers a and B (MSTPCRA and MSTPCRB)
713
Module Stop Control Register C (MSTPCRC)
716
Multi-Clock Function
717
Module Stop Mode
717
Sleep Mode
718
Transition to Sleep Mode
718
Clearing Sleep Mode
718
All-Module-Clock-Stop Mode
718
Software Standby Mode
719
Transition to Software Standby Mode
719
Clearing Software Standby Mode
719
Setting Oscillation Settling Time after Clearing Software Standby Mode
720
Table 19.2 Oscillation Settling Time Settings
720
Software Standby Mode Application Example
722
Figure 19.2 Software Standby Mode Application Example
722
Bφ Clock Output Control
723
Table 19.3 Bφ Pin (PA7) State in each Processing State
723
Usage Notes
724
I/O Port Status
724
Current Consumption During Oscillation Settling Standby Period
724
DMAC Module Stop
724
On-Chip Peripheral Module Interrupts
724
Writing to MSTPCRA, MSTPCRB, and MSTPCRC
724
Section 20 List of Registers
725
Register Addresses (Address Order)
726
Register Bits
749
Register States in each Operating Mode
776
Section 21 Electrical Characteristics
799
Absolute Maximum Ratings
799
Table 21.1 Absolute Maximum Ratings
799
DC Characteristics
800
Table 21.2 DC Characteristics (1)
800
Table 21.2 DC Characteristics (2)
801
AC Characteristics
802
Figure 21.1 Output Load Circuit
802
Table 21.3 Permissible Output Currents
802
Clock Timing
803
Figure 21.2 System Bus Clock Timing
803
Table 21.4 Clock Timing
803
Figure 21.3 Oscillation Settling Timing after Software Standby Mode
804
Figure 21.4 Oscillation Settling Timing
804
Figure 21.5 External Input Clock Timing
804
Control Signal Timing
805
Figure 21.6 Reset Input Timing
805
Table 21.5 Control Signal Timing
805
Timing of On-Chip Peripheral Modules
806
Figure 21.7 Interrupt Input Timing
806
Table 21.6 Timing of On-Chip Peripheral Modules (1)
806
Table 21.6 Timing of On-Chip Peripheral Modules (2)
808
Figure 21.8 I/O Port Input/Output Timing
809
Figure 21.9 Data Input Timing for Realtime Input Port
809
Figure 21.10 TPU Input/Output Timing
810
Figure 21.11 TPU Clock Input Timing
810
Figure 21.12 PPG Output Timing
810
Figure 21.13 SCK Clock Input/Output Timing
810
Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode
811
Figure 21.15 A/D Converter External Trigger Input Timing
811
Figure 21.16 HCAN Input/Output Timing
811
Figure 21.17 SSU Timing (Master, CPHS = 1)
812
Figure 21.18 SSU Timing (Master, CPHS = 0)
812
Figure 21.19 SSU Timing (Slave, CPHS = 1)
813
A/D Conversion Characteristics
814
Table 21.7 A/D Conversion Characteristics
814
Flash Memory Characteristics
815
Table 21.8 Flash Memory Characteristics
815
Appendix
817
Port States in each Pin State
817
Table A.1 Port States in each Pin State
817
Product Lineup
818
Package Dimensions
819
Main Revisions and Additions in this Edition
821
Index
837
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Renesas H8SX/1520 Series Hardware Manual (846 pages)
32-Bit CISC Microcomputer
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Table of Contents
Table of Contents
9
Table of Contents
33
Section 1 Overview
39
Features
39
Block Diagram
40
Figure 1.1 Block Diagram of H8SX/1527
40
Section 1 Overview
40
Figure 1.2 Block Diagram of H8SX/1525
41
Pin Assignments
42
Figure 1.3 Pin Assignments of H8SX/1527
42
Figure 1.4 Pin Assignments of H8SX/1525
43
Pin Configuration in each Operating Mode
44
Table 1.1 Pin Configuration in each Operating Mode
44
Pin Functions
48
Table 1.2 Pin Functions
48
Section 2 CPU
57
Features
57
Section 2 CPU
58
CPU Operating Modes
59
Normal Mode
59
Figure 2.1 CPU Operating Modes
59
Figure 2.2 Exception Vector Table (Normal Mode)
60
Figure 2.3 Stack Structure (Normal Mode)
60
Middle Mode
61
Advanced Mode
62
Figure 2.4 Exception Vector Table (Middle and Advanced Modes)
62
Maximum Mode
63
Figure 2.5 Stack Structure (Middle and Advanced Modes)
63
Figure 2.6 Exception Vector Table (Maximum Modes)
64
Figure 2.7 Stack Structure (Maximum Mode)
64
Instruction Fetch
65
Address Space
65
Figure 2.8 Memory Map
65
Registers
66
Figure 2.9 CPU Registers
66
General Registers
67
Figure 2.10 Usage of General Registers
67
Program Counter (PC)
68
Condition-Code Register (CCR)
68
Figure 2.11 Stack
68
Extended Control Register (EXR)
70
Vector Base Register (VBR)
70
Short Address Base Register (SBR)
70
Multiply-Accumulate Register (MAC)
71
Initial Values of CPU Registers
71
2Data Formats
71
General Register Data Formats
71
Figure 2.12 General Register Data Formats
72
Memory Data Formats
73
Figure 2.13 Memory Data Formats
73
Instruction Set
74
Table 2.1 Instruction Classification
74
Instructions and Addressing Modes
76
Table 2.2 Combinations of Instructions and Addressing Modes (1)
76
Table 2.2 Combinations of Instructions and Addressing Modes (2)
79
Table of Instructions Classified by Function
80
Table 2.3 Operation Notation
80
Table 2.4 Data Transfer Instructions
81
Table 2.5 Block Transfer Instructions
82
Table 2.6 Arithmetic Operation Instructions
83
Table 2.7 Logic Operation Instructions
85
Table 2.8 Shift Operation Instructions
86
Table 2.9 Bit Manipulation Instructions
87
Table 2.10 Branch Instructions
89
Table 2.11 System Control Instructions
90
Basic Instruction Formats
91
Figure 2.14 Instruction Formats
91
Addressing Modes and Effective Address Calculation
92
Table 2.12 Addressing Modes
92
Register Direct-Rn
93
Register Indirect-@Ern
93
Register Indirect with Displacement-@(D:2, Ern), @(D:16, Ern), or @(D:32, Ern)
93
Index Register Indirect with Displacement-@(D:16,Rnl.b), @(D:32,Rnl.b), @(D:16,Rn.w), @(D:32,Rn.w), @(D:16,Ern.l), or @(D:32,Ern.l)
94
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement-@Ern+, @−Ern, @+Ern, or @Ern
94
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
96
Table 2.13 Absolute Address Access Ranges
96
Immediate-#XX
97
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
97
Program-Counter Relative with Index Register- @(Rnl.b, PC), @(Rn.w, PC), or @(Ern.l, PC)
97
Memory Indirect-@@Aa:8
98
Figure 2.15 Branch Address Specification in Memory Indirect Mode
98
Extended Memory Indirect-@@Vec:7
99
Effective Address Calculation
99
Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
100
MOVA Instruction
101
Table 2.15 Effective Address Calculation for Branch Instructions
101
Processing States
102
Figure 2.16 State Transitions
103
Section 3 MCU Operating Modes
105
Operating Mode Selection
105
Register Descriptions
106
Mode Control Register (MDCR)
106
System Control Register (SYSCR)
107
Table 3.2 Settings of Bits MSD3 to MSD0
107
Operating Mode Descriptions
109
Mode 1
109
Mode 2
109
Mode 3
109
Address Map
110
Address Map (Advanced Mode)
110
Figure 3.1 Address Map (Advanced Mode)
110
Section 4 Exception Handling
111
Exception Handling Types and Priority
111
Table 4.1 Exception Types and Priority
111
Exception Sources and Exception Handling Vector Table
112
Table 4.2 Exception Handling Vector Table
112
Reset
114
Reset Exception Handling
114
Table 4.3 Calculation Method of Exception Handling Vector Table Address
114
Interrupts after Reset
115
On-Chip Peripheral Functions after Reset Release
115
Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)
115
Traces
116
Table 4.4 Status of CCR and EXR after Trace Exception Handling
116
Address Error
117
Address Error Source
117
Table 4.5 Bus Cycle and Address Error
117
Address Error Exception Handling
118
Interrupts
119
Interrupt Sources
119
Table 4.6 States of CCR and EXR after Address Error Exception Handling
119
Table 4.7 Interrupt Sources
119
Interrupt Exception Handling
120
Instruction Exception Handling
121
Trap Instruction
121
Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling
121
Exception Handling by Illegal Instruction
122
Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling
122
Stack Status after Exception Handling
123
Figure 4.2 Stack Status after Exception Handling
123
Usage Note
124
Figure 4.3 Operation When SP Value Is Odd
124
Section 5 Interrupt Controller
125
Features
125
Input/Output Pins
126
Figure 5.1 Block Diagram of Interrupt Controller
126
Register Descriptions
127
Interrupt Control Register (INTCR)
127
CPU Priority Control Register (CPUPCR)
128
Interrupt Priority Registers a to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR)
130
IRQ Enable Register (IER)
132
IRQ Sense Control Registers H and L (ISCRH and ISCRL)
134
IRQ Status Register (ISR)
139
Software Standby Release IRQ Enable Register (SSIER)
140
Interrupt Sources
141
External Interrupts
141
Internal Interrupts
142
Figure 5.2 Block Diagram of Interrupts Irqn
142
Interrupt Exception Handling Vector Table
143
Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority
143
Interrupt Control Modes and Interrupt Operation
150
Interrupt Control Mode 0
150
Table 5.3 Interrupt Control Modes
150
Interrupt Control Mode 2
152
Interrupt Exception Handling Sequence
154
Figure 5.5 Interrupt Exception Handling
154
Interrupt Response Times
155
Table 5.4 Interrupt Response Times
155
DMAC Activation by Interrupt
156
Figure 5.6 Block Diagram of DMAC and Interrupt Controller
156
Table 5.5 Number of Execution States in Interrupt Handling Routine
156
Table 5.6 Interrupt Source Selection and Clear Control
157
CPU Priority Control Function over DMAC
158
Table 5.7 CPU Priority Control
159
Table 5.8 Example of Priority Control Function Setting and Control State
159
Usage Notes
160
Conflict between Interrupt Generation and Disabling
160
Figure 5.7 Conflict between Interrupt Generation and Disabling
160
Instructions that Disable Interrupts
161
Times When Interrupts Are Disabled
161
Interrupts During Execution of EEPMOV Instruction
161
Interrupts During Execution of MOVMD and MOVSD Instructions
161
Interrupt Flags of Peripheral Modules
162
Section 6 Bus Controller (BSC)
163
Features
163
Figure 6.1 Block Diagram of Bus Controller
163
Register Descriptions
164
Bus Control Register 2 (BCR2)
164
Bus Configuration
165
Figure 6.2 Internal Bus Configuration
165
Multi-Clock Function
166
Table 6.1 Synchronization Clocks and Their Corresponding Functions
166
Internal Bus
167
Access to Internal Address Space
167
Table 6.2 Number of Access Cycles for On-Chip Memory Spaces
167
Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules
167
Write Data Buffer Function
168
Write Data Buffer Function for Peripheral Module
168
Figure 6.3 Example of Timing When Write Data Buffer Function Is Used
168
Bus Arbitration
169
Operation
169
Bus Transfer Timing
169
Bus Controller Operation in Reset
170
Usage Notes
170
Section 7 DMA Controller (DMAC)
171
Features
171
Figure 7.1 Block Diagram of DMAC
173
Register Descriptions
174
DMA Source Address Register (DSAR)
175
DMA Destination Address Register (DDAR)
176
DMA Offset Register (DOFR)
177
DMA Transfer Count Register (DTCR)
178
DMA Block Size Register (DBSR)
179
DMA Mode Control Register (DMDR)
180
DMA Address Control Register (DACR)
189
Table 7.2 Settings and Areas of Extended Repeat Area
194
DMA Module Request Select Register (DMRSR)
195
Transfer Modes
195
Table 7.3 Transfer Modes
195
Operations
196
Address Modes
196
Figure 7.2 Example of Signal Timing in Dual Address Mode
197
Figure 7.3 Operations in Dual Address Mode
197
Figure 7.4 Data Flow in Single Address Mode
198
Figure 7.5 Example of Signal Timing in Single Address Mode
199
Figure 7.6 Operations in Single Address Mode
199
Transfer Modes
200
Figure 7.7 Example of Signal Timing in Normal Transfer Mode
200
Figure 7.8 Operations in Normal Transfer Mode
200
Figure 7.9 Operations in Repeat Transfer Mode
201
Figure 7.10 Operations in Block Transfer Mode
202
Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified)
203
Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified)
203
Activation Sources
204
Table 7.4 List of On-Chip Module Interrupts to DMAC
205
Bus Access Modes
206
Figure 7.13 Example of Timing in Cycle Stealing Mode
207
Figure 7.14 Example of Timing in Burst Mode
207
Extended Repeat Area Function
208
Figure 7.15 Example of Extended Repeat Area Operation
209
Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode
209
Address Update Function Using Offset
210
Figure 7.17 Address Update Method
210
Figure 7.18 Operation of Offset Addition
211
Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
212
Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
213
Register During DMA Transfer
214
Figure 7.21 Procedure for Changing Register Setting for Channel Being Transferred
217
Priority of Channels
219
Figure 7.22 Example of Timing for Channel Priority
219
Table 7.5 Priority Among DMAC Channels
219
DMA Basic Bus Cycle
220
Figure 7.23 Example of Bus Timing of DMA Transfer
220
Bus Cycles in Dual Address Mode
221
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
221
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment)
222
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement)
222
Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access
223
Figure 7.28 Example of Transfer in Block Transfer Mode
224
Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge
225
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level
226
Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level
227
Figure 7.32 Example of Transfer in Normal Transfer Mode Activated
228
Bus Cycles in Single Address Mode
229
Figure 7.33 Example of Transfer in Single Address Mode (Byte Read)
229
Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)
230
Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge
231
Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level
232
Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1
233
DMA Transfer End
234
Relationship Among DMAC and Other Bus Masters
236
CPU Priority Control Function over DMAC
236
Bus Arbitration Among DMAC and Other Bus Masters
237
Interrupt Sources
238
Table 7.6 Interrupt Sources and Priority
238
Figure 7.38 Interrupt and Interrupt Sources
240
Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source
240
Notes on Usage
241
Section 8 I/O Ports
243
Table 8.1 Port Functions
243
Register Descriptions
248
Table 8.2 Register Configuration in each Port
248
Figure 8.1 Port Block Diagram
249
Data Direction Register (Pnddr) (N = 1 to 3, 6, A, D, H, J, and K)
250
Data Register (Pndr) (N = 1 to 3, 6, A, D, H, J, and K)
250
Port Register (Portn) (N = 1 to 6, A, D, H, J, and K)
251
Input Buffer Control Register (Pnicr) (N = 1 to 6, A, D, H, J, and K)
251
Pull-Up MOS Control Register (Pnpcr) (N = D, H, J, and K)
252
Table 8.3 Input Pull-Up MOS State
252
Open-Drain Control Register (Pnodr) (N = 2)
253
Port H Realtime Input Data Register (PHRTIDR)
253
Output Buffer Control
254
Port 1
254
Port 2
257
Port 3
259
Port 6
263
Port a
265
Port D
268
Port H
271
Port J
271
Port K
274
Table 8.4 Available Output Signals and Settings in each Port
277
Port Function Controller
281
Port Function Control Register 9 (PFCR9)
281
Port Function Control Register a (PFCRA)
283
Port Function Control Register B (PFCRB)
285
Usage Notes
287
Notes on Input Buffer Control Register (ICR) Setting
287
Notes on Port Function Control Register (PFCR) Settings
287
Section 9 16-Bit Timer Pulse Unit (TPU)
289
Features
289
Table 9.1 Unit Configuration for each Product
290
Table 9.2 TPU Functions (Unit 0)
290
Table 9.3 TPU Functions (Unit 1)
292
Figure 9.1 Block Diagram of TPU (Unit 0)
294
Figure 9.2 Block Diagram of TPU (Unit 1)
295
Input/Output Pins
296
Table 9.4 Pin Configuration
296
Register Descriptions
298
Timer Control Register (TCR)
303
Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3)
304
Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
304
Table 9.7 Input Clock Edge Selection
305
Table 9.8 TPSC2 to TPSC0 (Channel 0)
305
Table 9.9 TPSC2 to TPSC0 (Channel 1)
305
Table 9.10 TPSC2 to TPSC0 (Channel 2)
306
Table 9.11 TPSC2 to TPSC0 (Channel 3)
306
Table 9.12 TPSC2 to TPSC0 (Channel 4)
307
Table 9.13 TPSC2 to TPSC0 (Channel 5)
307
Timer Mode Register (TMDR)
308
Table 9.14 MD3 to MD0
309
Timer I/O Control Register (TIOR)
310
Table 9.15 TIORH_0
312
Table 9.16 TIORL_0
313
Table 9.17 TIOR_1
314
Table 9.18 TIOR_2
315
Table 9.19 TIORH_3
316
Table 9.20 TIORL_3
317
Table 9.21 TIOR_4
318
Table 9.22 TIOR_5
319
Table 9.23 TIORH_0
320
Table 9.24 TIORL_0
321
Table 9.25 TIOR_1
322
Table 9.26 TIOR_2
323
Table 9.27 TIORH_3
324
Table 9.28 TIORL_3
325
Table 9.29 TIOR_4
326
Table 9.30 TIOR_5
327
Timer Interrupt Enable Register (TIER)
328
Timer Status Register (TSR)
330
Timer Counter (TCNT)
334
Timer General Register (TGR)
334
Timer Start Register (TSTR)
335
Timer Synchronous Register (TSYR)
336
Operation
337
Basic Functions
337
Figure 9.3 Example of Counter Operation Setting Procedure
337
Figure 9.4 Free-Running Counter Operation
338
Figure 9.5 Periodic Counter Operation
339
Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match
339
Figure 9.7 Example of 0-Output/1-Output Operation
340
Figure 9.8 Example of Toggle Output Operation
340
Figure 9.9 Example of Setting Procedure for Input Capture Operation
341
Figure 9.10 Example of Input Capture Operation
342
Synchronous Operation
343
Figure 9.11 Example of Synchronous Operation Setting Procedure
343
Figure 9.12 Example of Synchronous Operation
344
Buffer Operation
345
Figure 9.13 Compare Match Buffer Operation
345
Table 9.31 Register Combinations in Buffer Operation
345
Figure 9.14 Input Capture Buffer Operation
346
Figure 9.15 Example of Buffer Operation Setting Procedure
346
Figure 9.16 Example of Buffer Operation (1)
347
Figure 9.17 Example of Buffer Operation (2)
348
Cascaded Operation
349
Figure 9.18 Example of Cascaded Operation Setting Procedure
349
Table 9.32 Cascaded Combinations
349
Figure 9.19 Example of Cascaded Operation (1)
350
Figure 9.20 Example of Cascaded Operation (2)
350
PWM Modes
351
Table 9.33 PWM Output Registers and Output Pins
352
Figure 9.21 Example of PWM Mode Setting Procedure
353
Figure 9.22 Example of PWM Mode Operation (1)
354
Figure 9.23 Example of PWM Mode Operation (2)
354
Figure 9.24 Example of PWM Mode Operation (3)
355
Phase Counting Mode
356
Table 9.34 Clock Input Pins in Phase Counting Mode
356
Figure 9.25 Example of Phase Counting Mode Setting Procedure
357
Figure 9.26 Example of Phase Counting Mode 1 Operation
358
Table 9.35 Up/Down-Count Conditions in Phase Counting Mode 1
358
Figure 9.27 Example of Phase Counting Mode 2 Operation
359
Table 9.36 Up/Down-Count Conditions in Phase Counting Mode 2
359
Figure 9.28 Example of Phase Counting Mode 3 Operation
360
Table 9.37 Up/Down-Count Conditions in Phase Counting Mode 3
360
Figure 9.29 Example of Phase Counting Mode 4 Operation
361
Table 9.38 Up/Down-Count Conditions in Phase Counting Mode 4
361
Figure 9.30 Phase Counting Mode Application Example
363
Interrupt Sources
364
Table 9.39 TPU Interrupts
364
DMAC Activation
367
A/D Converter Activation
367
Operation Timing
368
Input/Output Timing
368
Figure 9.31 Count Timing in Internal Clock Operation
368
Figure 9.32 Count Timing in External Clock Operation
368
Figure 9.33 Output Compare Output Timing
369
Figure 9.34 Input Capture Input Signal Timing
369
Figure 9.35 Counter Clear Timing (Compare Match)
370
Figure 9.36 Counter Clear Timing (Input Capture)
370
Figure 9.37 Buffer Operation Timing (Compare Match)
371
Figure 9.38 Buffer Operation Timing (Input Capture)
371
Interrupt Signal Timing
372
Figure 9.39 TGI Interrupt Timing (Compare Match)
372
Figure 9.40 TGI Interrupt Timing (Input Capture)
372
Figure 9.41 TCIV Interrupt Setting Timing
373
Figure 9.42 TCIU Interrupt Setting Timing
373
Figure 9.43 Timing for Status Flag Clearing by CPU
374
Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)
374
Usage Notes
375
Module Stop Mode Setting
375
Input Clock Restrictions
375
Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)
375
Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
375
Caution on Cycle Setting
376
Conflict between TCNT Write and Clear Operations
376
Figure 9.47 Conflict between TCNT Write and Clear Operations
376
Conflict between TCNT Write and Increment Operations
377
Conflict between TGR Write and Compare Match
377
Figure 9.48 Conflict between TCNT Write and Increment Operations
377
Figure 9.49 Conflict between TGR Write and Compare Match
377
Conflict between Buffer Register Write and Compare Match
378
Conflict between TGR Read and Input Capture
378
Figure 9.50 Conflict between Buffer Register Write and Compare Match
378
Figure 9.51 Conflict between TGR Read and Input Capture
378
Conflict between TGR Write and Input Capture
379
Conflict between Buffer Register Write and Input Capture
379
Figure 9.52 Conflict between TGR Write and Input Capture
379
Figure 9.53 Conflict between Buffer Register Write and Input Capture
379
Conflict between Overflow/Underflow and Counter Clearing
380
Conflict between TCNT Write and Overflow/Underflow
380
Figure 9.54 Conflict between Overflow and Counter Clearing
380
Figure 9.55 Conflict between TCNT Write and Overflow
380
Multiplexing of I/O Pins
381
Interrupts and Module Stop Mode
381
Section 10 Programmable Pulse Generator (PPG)
383
Features
383
Figure 10.1 Block Diagram of PPG
383
Input/Output Pins
384
Table 10.1 Pin Configuration
384
Register Descriptions
385
Next Data Enable Registers H, L (NDERH, NDERL)
385
Output Data Registers H, L (PODRH, PODRL)
387
Next Data Registers H, L (NDRH, NDRL)
388
PPG Output Control Register (PCR)
391
PPG Output Mode Register (PMR)
392
Operation
394
Output Timing
394
Figure 10.2 Schematic Diagram of PPG
394
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)
394
Sample Setup Procedure for Normal Pulse Output
395
Figure 10.4 Setup Procedure for Normal Pulse Output (Example)
395
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)
396
Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output)
396
Non-Overlapping Pulse Output
397
Figure 10.6 Non-Overlapping Pulse Output
397
Figure 10.7 Non-Overlapping Operation and NDR Write Timing
398
Sample Setup Procedure for Non-Overlapping Pulse Output
399
Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
399
Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)
400
Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary)
400
Inverted Pulse Output
402
Figure 10.10 Inverted Pulse Output (Example)
402
Pulse Output Triggered by Input Capture
403
Usage Notes
403
Module Stop Mode Setting
403
Operation of Pulse Output Pins
403
Figure 10.11 Pulse Output Triggered by Input Capture (Example)
403
Section 11 Watchdog Timer (WDT)
405
Features
405
Figure 11.1 Block Diagram of WDT
405
Register Descriptions
406
Timer Counter (TCNT)
406
Timer Control/Status Register (TCSR)
407
Reset Control/Status Register (RSTCSR)
408
Operation
410
Watchdog Timer Mode
410
Figure 11.2 Operation in Watchdog Timer Mode
410
Interval Timer Mode
411
Interrupt Source
411
Figure 11.3 Operation in Interval Timer Mode
411
Table 11.1 WDT Interrupt Source
411
Usage Notes
412
Notes on Register Access
412
Figure 11.4 Writing to TCNT, TCSR, and RSTCSR
412
Conflict between Timer Counter (TCNT) Write and Increment
413
Changing Values of Bits CKS2 to CKS0
413
Switching between Watchdog Timer Mode and Interval Timer Mode
413
Figure 11.5 Conflict between TCNT Write and Increment
413
Transition to Watchdog Timer Mode or Software Standby Mode
414
Section 12 Serial Communication Interface (SCI)
415
Features
415
Figure 12.1 Block Diagram of SCI
416
Input/Output Pins
417
Table 12.1 Pin Configuration
417
Register Descriptions
418
Receive Shift Register (RSR)
419
Receive Data Register (RDR)
419
Transmit Data Register (TDR)
419
Transmit Shift Register (TSR)
420
Serial Mode Register (SMR)
420
Serial Control Register (SCR)
423
Serial Status Register (SSR)
427
Smart Card Mode Register (SCMR)
435
Bit Rate Register (BRR)
436
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
436
Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
437
Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
438
Table 12.4 Maximum Bit Rate for each Operating Frequency (Asynchronous Mode)
439
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
439
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
440
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
441
Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, N = 0, S = 372)
442
Table 12.9 Maximum Bit Rate for each Operating Frequency (Smart Card Interface Mode, S = 372)
442
Operation in Asynchronous Mode
443
Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
443
Data Transfer Format
444
Table 12.10 Serial Transfer Formats (Asynchronous Mode)
444
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
445
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
445
Clock
446
Figure 12.4 Phase Relation between Output Clock and Transmit Data
446
SCI Initialization (Asynchronous Mode)
447
Figure 12.5 Sample SCI Initialization Flowchart
447
Serial Data Transmission (Asynchronous Mode)
448
Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
448
Figure 12.7 Sample Serial Transmission Flowchart
449
Serial Data Reception (Asynchronous Mode)
450
Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit)
450
Table 12.11 SSR Status Flags and Receive Data Handling
451
Figure 12.9 Sample Serial Reception Flowchart (1)
452
Figure 12.9 Sample Serial Reception Flowchart (2)
453
Multiprocessor Communication Function
454
Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
455
Multiprocessor Serial Data Transmission
456
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
456
Multiprocessor Serial Data Reception
457
Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
457
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
458
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
459
Operation in Clocked Synchronous Mode
460
Clock
460
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)
460
SCI Initialization (Clocked Synchronous Mode)
461
Figure 12.15 Sample SCI Initialization Flowchart
461
Serial Data Transmission (Clocked Synchronous Mode)
462
Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode
463
Figure 12.17 Sample Serial Transmission Flowchart
463
Serial Data Reception (Clocked Synchronous Mode)
464
Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode
464
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
465
Figure 12.19 Sample Serial Reception Flowchart
465
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
466
Operation in Smart Card Interface Mode
467
Sample Connection
467
Figure 12.21 Pin Connection for Smart Card Interface
467
Data Format (Except in Block Transfer Mode)
468
Figure 12.22 Data Formats in Normal Smart Card Interface Mode
468
Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0)
468
Block Transfer Mode
469
Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)
469
Receive Data Sampling Timing and Reception Margin
470
Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate)
470
Initialization
471
Data Transmission (Except in Block Transfer Mode)
472
Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode
473
Figure 12.27 TEND Flag Set Timing During Transmission
473
Figure 12.28 Sample Transmission Flowchart
474
Serial Data Reception (Except in Block Transfer Mode)
475
Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode
475
Clock Output Control
476
Figure 12.30 Sample Reception Flowchart
476
Figure 12.31 Clock Output Fixing Timing
476
Figure 12.32 Clock Stop and Restart Procedure
477
Interrupt Sources
478
Interrupts in Normal Serial Communication Interface Mode
478
Table 12.12 SCI Interrupt Sources
478
Interrupts in Smart Card Interface Mode
479
Table 12.13 SCI Interrupt Sources
479
Usage Notes
480
Module Stop Mode Setting
480
Break Detection and Processing
480
Mark State and Break Detection
480
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
480
Relation between Writing to TDR and TDRE Flag
481
Restrictions on Using DMAC
481
Figure 12.33 Sample Transmission Using DMAC in Clocked Synchronous Mode
481
SCI Operations During Mode Transitions
482
Figure 12.34 Sample Flowchart for Mode Transition During Transmission
483
Figure 12.35 Port Pin States During Mode Transition (Internal Clock, Asynchronous Transmission)
484
Figure 12.36 Port Pin States During Mode Transition (Internal Clock, Clocked Synchronous Transmission)
484
Figure 12.37 Sample Flowchart for Mode Transition During Reception
485
Section 13 Controller Area Network (HCAN)
487
Features
487
Figure 13.1 HCAN Block Diagram
488
Input/Output Pins
489
Table 13.1 Pin Configuration
489
Register Descriptions
490
Master Control Register (MCR)
491
General Status Register (GSR)
492
Bit Configuration Register (BCR)
494
Mailbox Configuration Register (MBCR)
496
Transmit Wait Register (TXPR)
497
Transmit Wait Cancel Register (TXCR)
498
Transmit Acknowledge Register (TXACK)
499
Abort Acknowledge Register (ABACK)
500
Receive Complete Register (RXPR)
501
Remote Request Register (RFPR)
502
Interrupt Register (IRR)
503
Mailbox Interrupt Mask Register (MBIMR)
508
Interrupt Mask Register (IMR)
509
Receive Error Counter (REC)
511
Transmit Error Counter (TEC)
511
Unread Message Status Register (UMSR)
512
Local Acceptance Filter Masks (LAFML, LAFMH)
513
Message Control (MC0 to MC15)
516
Figure 13.2 Message Control Register Configuration
516
Figure 13.3 Standard Format
516
Figure 13.4 Extended Format
516
Message Data (MD0 to MD15)
519
Figure 13.5 Message Data Configuration
519
HCAN Monitor Register (HCANMON)
521
Operation
522
Hardware and Software Resets
522
Initialization after Hardware Reset
522
Figure 13.6 Hardware Reset Flowchart
523
Figure 13.7 Software Reset Flowchart
524
Figure 13.8 Detailed Description of One Bit
525
Table 13.2 Limits for the Settable Value
525
Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR
526
Message Transmission
528
Figure 13.9 Transmission Flowchart
528
Figure 13.10 Transmit Message Cancellation Flowchart
531
Message Reception
532
Figure 13.11 Reception Flowchart
532
Figure 13.12 Unread Message Overwrite Flowchart
535
HCAN Sleep Mode
536
Figure 13.13 HCAN Sleep Mode Flowchart
536
HCAN Halt Mode
538
Figure 13.14 HCAN Halt Mode Flowchart
538
Interrupt Sources
539
Table 13.4 HCAN Interrupt Sources
539
DMAC Interface
540
Figure 13.15 DMAC Transfer Flowchart
540
CAN Bus Interface
541
Figure 13.16 High-Speed Interface Using PCA82C250
541
Usage Notes
542
Module Stop Mode Setting
542
Reset
542
HCAN Sleep Mode
542
Interrupts
543
Error Counters
543
Register Access
543
Register Hold in Standby Modes
543
Use on Bit Manipulation Instructions
543
HCAN TXCR Operation
544
13.8.10 HCAN Transmission Setting
545
13.8.11 Canceling HCAN Reset and HCAN Sleep Mode
545
13.8.12 Accessing Mailbox in HCAN Sleep Mode
545
Table 13.5 Duration between Transmission Setting
545
Section 14 Synchronous Serial Communication Unit (SSU)
547
Features
547
Figure 14.1 Block Diagram of SSU
548
Input/Output Pins
549
Table 14.1 Pin Configuration
549
Register Descriptions
550
SS Control Register H (SSCRH)
552
SS Control Register L (SSCRL)
554
SS Mode Register (SSMR)
555
SS Enable Register (SSER)
556
SS Status Register (SSSR)
557
SS Control Register 2 (SSCR2)
559
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
561
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
562
Table 14.2 Correspondence between DATS Bit Setting and SSTDR
562
SS Shift Register (SSTRSR)
563
Table 14.3 Correspondence between DATS Bit Setting and SSRDR
563
Operation
564
Transfer Clock
564
Relationship of Clock Phase, Polarity, and Data
564
Figure 14.2 Relationship of Clock Phase, Polarity, and Data
564
Relationship between Data Input/Output Pins and Shift Register
565
Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register
565
Communication Modes and Pin Functions
566
Table 14.4 Communication Modes and Pin States of SSI and SSO Pins
566
Table 14.5 Communication Modes and Pin States of SSCK Pin
567
Table 14.6 Communication Modes and Pin States of SCS Pin
567
SSU Mode
568
Figure 14.4 Example of Initial Settings in SSU Mode
568
Figure 14.5 Example of Transmission Operation (SSU Mode)
570
Figure 14.6 Flowchart Example of Data Transmission (SSU Mode)
571
Figure 14.7 Example of Reception Operation (SSU Mode)
573
Figure 14.8 Flowchart Example of Data Reception (SSU Mode)
574
Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
575
SCS Pin Control and Conflict Error
576
Figure 14.10 Conflict Error Detection Timing (before Transfer)
576
Figure 14.11 Conflict Error Detection Timing (after Transfer End)
576
Clock Synchronous Communication Mode
577
Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode
577
Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode)
578
Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)
579
Figure 14.15 Example of Reception Operation
580
Figure 14.16 Flowchart Example of Data Reception
581
Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)
582
Interrupt Requests
583
Table 14.7 Interrupt Sources
583
Usage Note
584
Setting of Module Stop Mode
584
Notes on Clearing Module Stop Mode
584
Section 15 A/D Converter
585
Features
585
Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)
587
Input/Output Pins
588
Table 15.1 Pin Configuration
588
Register Descriptions
589
A/D Data Registers a to H (ADDRA to ADDRH)
590
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
590
A/D Control/Status Register (ADCSR)
591
A/D Control Register (ADCR)
593
Operation
594
Single Mode
594
Scan Mode
595
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
595
Figure 15.4 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected)
596
Input Sampling and A/D Conversion Time
597
Figure 15.5 A/D Conversion Timing
597
External Trigger Input Timing
598
Figure 15.6 External Trigger Input Timing
598
Table 15.3 A/D Conversion Characteristics (Single Mode)
598
Table 15.4 A/D Conversion Characteristics (Scan Mode)
598
Interrupt Source
599
A/D Conversion Accuracy Definitions
599
Table 15.5 A/D Converter Interrupt Source
599
Figure 15.7 A/D Conversion Accuracy Definitions
600
Figure 15.8 A/D Conversion Accuracy Definitions
600
Usage Notes
601
Module Stop Mode Setting
601
Permissible Signal Source Impedance
601
Figure 15.9 Example of Analog Input Circuit
601
Influences on Absolute Accuracy
602
Setting Range of Analog Power Supply and Other Pins
602
Notes on Board Design
602
Notes on Noise Countermeasures
603
Figure 15.10 Example of Analog Input Protection Circuit
603
Table 15.6 Analog Pin Specifications
603
A/D Input Hold Function in Software Standby Mode
604
Figure 15.11 Analog Input Pin Equivalent Circuit
604
Section 16 RAM
605
Section 17 Flash Memory (0.18-ΜM F-ZTAT Version)
607
Features
607
Figure 17.1 Block Diagram of Flash Memory
608
Mode Transition Diagram
609
Figure 17.2 Mode Transition of Flash Memory
609
Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode
610
Memory MAT Configuration
611
Figure 17.3 Memory MAT Configuration
611
Block Structure
612
Figure 17.4 Block Structure of User MAT
612
Programming/Erasing Interface
613
Figure 17.5 Procedure for Creating Procedure Program
613
Input/Output Pins
615
Table 17.2 Pin Configuration
615
Register Descriptions
616
Programming/Erasing Interface Registers
617
Table 17.3 Registers/Parameters and Target Modes
617
Programming/Erasing Interface Parameters
624
Table 17.4 Parameters and Target Modes
624
RAM Emulation Register (RAMER)
636
On-Board Programming Mode
637
Boot Mode
637
Figure 17.6 System Configuration in Boot Mode
637
Table 17.5 On-Board Programming Mode Setting
637
Figure 17.7 Automatic-Bit-Rate Adjustment Operation
638
Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
638
Figure 17.8 Boot Mode State Transition Diagram
639
User Program Mode
641
Figure 17.9 Programming/Erasing Flow
641
Figure 17.10 RAM Map When Programming/Erasing Is Executed
642
Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode
650
User Boot Mode
651
On-Chip Program and Storable Area for Program Data
655
Table 17.7 Executable Memory MAT
656
Table 17.8 Usable Area for Programming in User Program Mode
657
Table 17.9 Usable Area for Erasure in User Program Mode
658
Table 17.10 Usable Area for Programming in User Boot Mode
659
Table 17.11 Usable Area for Erasure in User Boot Mode
660
Protection
661
Hardware Protection
661
Table 17.12 Hardware Protection
661
Software Protection
662
Error Protection
662
Table 17.13 Software Protection
662
Figure 17.16 Transitions to Error Protection State
663
Flash Memory Emulation Using RAM
664
Figure 17.17 RAM Emulation Flow
664
Figure 17.18 Address Map of Overlaid RAM Area
665
Figure 17.19 Programming Tuned Data
666
Switching between User MAT and User Boot MAT
667
Programmer Mode
668
Standard Serial Communication Interface Specifications for Boot Mode
668
Table 17.14 Device Types Supported in Programmer Mode
668
Figure 17.21 Boot Program States
669
Figure 17.22 Bit-Rate-Adjustment Sequence
670
Figure 17.23 Communication Protocol Format
671
Table 17.15 Inquiry and Selection Commands
672
Figure 17.24 New Bit-Rate Selection Sequence
682
Table 17.16 Programming/Erasing Commands
685
Figure 17.25 Programming Sequence
686
Figure 17.26 Erasure Sequence
687
Table 17.17 Status Code
695
Table 17.18 Error Code
695
Usage Notes
696
Section 18 Clock Pulse Generator
699
Figure 18.1 Block Diagram of Clock Pulse Generator
699
Register Description
700
System Clock Control Register (SCKCR)
700
Oscillator
703
Connecting Crystal Resonator
703
Figure 18.2 Connection of Crystal Resonator (Example)
703
Figure 18.3 Crystal Resonator Equivalent Circuit
703
Table 18.1 Damping Resistance Value
703
External Clock Input
704
PLL Circuit
704
Frequency Divider
704
Figure 18.4 External Clock Input (Examples)
704
Table 18.2 Crystal Resonator Characteristics
704
Usage Notes
705
Notes on Clock Pulse Generator
705
Figure 18.5 Clock Modification Timing
705
Notes on Resonator
706
Notes on Board Design
706
Figure 18.6 Note on Board Design for Oscillation Circuit
706
Notes on Input Clock Frequency
707
Figure 18.7 Connection Example of Bypass Capacitor
707
Section 19 Power-Down Modes
709
Features
709
Table 19.1 Operating States
709
Register Descriptions
710
Figure 19.1 Mode Transitions
710
Standby Control Register (SBYCR)
711
Module Stop Control Registers a and B (MSTPCRA and MSTPCRB)
713
Module Stop Control Register C (MSTPCRC)
716
Multi-Clock Function
717
Module Stop Mode
717
Sleep Mode
718
Transition to Sleep Mode
718
Clearing Sleep Mode
718
All-Module-Clock-Stop Mode
718
Software Standby Mode
719
Transition to Software Standby Mode
719
Clearing Software Standby Mode
719
Setting Oscillation Settling Time after Clearing Software Standby Mode
720
Table 19.2 Oscillation Settling Time Settings
720
Software Standby Mode Application Example
722
Figure 19.2 Software Standby Mode Application Example
722
Bφ Clock Output Control
723
Table 19.3 Bφ Pin (PA7) State in each Processing State
723
Usage Notes
724
I/O Port Status
724
Current Consumption During Oscillation Settling Standby Period
724
DMAC Module Stop
724
On-Chip Peripheral Module Interrupts
724
Writing to MSTPCRA, MSTPCRB, and MSTPCRC
724
Section 20 List of Registers
725
Register Addresses (Address Order)
726
Register Bits
749
Register States in each Operating Mode
776
Section 21 Electrical Characteristics
799
Absolute Maximum Ratings
799
Table 21.1 Absolute Maximum Ratings
799
DC Characteristics
800
Table 21.2 DC Characteristics (1)
800
Table 21.2 DC Characteristics (2)
801
AC Characteristics
802
Figure 21.1 Output Load Circuit
802
Table 21.3 Permissible Output Currents
802
Clock Timing
803
Figure 21.2 System Bus Clock Timing
803
Table 21.4 Clock Timing
803
Figure 21.3 Oscillation Settling Timing after Software Standby Mode
804
Figure 21.4 Oscillation Settling Timing
804
Figure 21.5 External Input Clock Timing
804
Control Signal Timing
805
Figure 21.6 Reset Input Timing
805
Table 21.5 Control Signal Timing
805
Timing of On-Chip Peripheral Modules
806
Table 21.6 Timing of On-Chip Peripheral Modules (1)
806
Table 21.6 Timing of On-Chip Peripheral Modules (2)
808
Figure 21.8 I/O Port Input/Output Timing
809
Figure 21.9 Data Input Timing for Realtime Input Port
809
Figure 21.10 TPU Input/Output Timing
810
Figure 21.11 TPU Clock Input Timing
810
Figure 21.12 PPG Output Timing
810
Figure 21.13 SCK Clock Input/Output Timing
810
Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode
811
Figure 21.15 A/D Converter External Trigger Input Timing
811
Figure 21.16 HCAN Input/Output Timing
811
Figure 21.17 SSU Timing (Master, CPHS = 1)
812
Figure 21.18 SSU Timing (Master, CPHS = 0)
812
Figure 21.19 SSU Timing (Slave, CPHS = 1)
813
A/D Conversion Characteristics
814
Table 21.7 A/D Conversion Characteristics
814
Flash Memory Characteristics
815
Table 21.8 Flash Memory Characteristics
815
Appendix
817
Port States in each Pin State
817
Table A.1 Port States in each Pin State
817
Product Lineup
818
Package Dimensions
819
Main Revisions and Additions in this Edition
821
Figure 17.11 Programming Procedure in User Program Mode
830
Figure 17.12 Erasing Procedure in User Program Mode
831
Figure 17.14 Procedure for Programming User MAT in User Boot Mode
832
Figure 17.15 Procedure for Erasing User MAT in User Boot Mode
832
Figure 17.20 Switching between User MAT and User Boot MAT
832
Figure 21.7 Interrupt Input Timing
836
Index
837
Renesas H8SX/1520 Series User Manual (23 pages)
Renesas User System Interface Cable User's Manual
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.21 MB
Table of Contents
Table of Contents
4
Section 1 Configuration
5
Section 2 Connection Procedures
7
Connecting User System Interface Cable to Emulator Station
7
Connecting User System Interface Cable to User System
9
Installing IC Socket
9
Soldering IC Socket
9
Inserting Cable Head
10
Fastening Cable Head
10
Fastening Cable Body
12
Recommended Dimensions for User System Mount Pad
13
Dimensions for User System Interface Cable Head
14
Resulting Dimensions after Connecting User System Interface Cable
15
Section 3 Installing the MCU to the User System
16
Section 4 Verifying Operation
18
Section 5 Notice
19
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