Renesas H8S Series Hardware Manual page 63

Type Symbol
LPC LAD3 to
Interface LAD0
(LPC)
LFRAME
LRESET
LCLK
SERIRQ
LSCI
LSMI
PME
GA20
CLKRUN
LPCPD
LID3
DLAD3 to
DLAD0
DLFRAME 117
DSERIRQ
DCLKRUN 137
LDRQ
DLDRQ
Pin No. I/O
124 to 121 Input/
Output
125 Input
126 Input
127 Input
128 Input/
Output
119 Input/
120 Output
129
130 Output
131 Input/
Output
132 Input
32 Input
116 to 113 Input/
Output
Output
136 Input/
Output
Input/
Output
88 Output
87 Input
Name and Function
Transfer cycle type, address, and data
input/output pins
Input pin indicating transfer cycle start and forced
termination of an abnormal transfer cycle
LPC reset pin. When this pin is low, a reset state
is entered.
LPC clock input pin
LPC serial host interrupt (HIRQ1, SMI, HIRQ6, or
HIRQ9 to HIRQ12) input/output pin
General input/output ports of LSCI, LSMI, and
PME
GATE A20 control signal output pin
LCLK operation start request input/output pin
LPC module shutdown control input pin
Input pin for setting host address 31
LAD input/output pins for the docking LPC
LFRAME output pin for the docking LPC
SERIRQ input/output pin for the docking LPC
CLKRUN input/output pin for the docking LPC
Encoded DMA request output pin for the docking
LPC
Encoded DMA request input pin for the docking
LPC
Rev. 3.00 Jul. 14, 2005 Page 15 of 986
Section 1 Overview
REJ09B0098-0300