Clock Output Control; Figure 15.31 Clock Output Fixing Timing - Renesas H8S Series Hardware Manual

Section 15 Serial Communication Interface (SCI, IrDA)
15.7.8

Clock Output Control

Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty ratio.
• At Power-On:
To secure the appropriate clock duty ratio simultaneously with power-on, use the following
procedure.
A. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
B. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
C. Set SMR and SCMR to enable smart card interface mode.
D. Set the CKE0 bit in SCR to 1 to start clock output.
• At Transition from Smart Card Interface Mode to Software Standby Mode:
A. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK
pins to the values for the output fixed state in software standby mode.
B. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set
the CKE1 bit to the value for the output fixed state in software standby mode.
C. Write 0 to the CKE0 bit in SCR to stop the clock.
D. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
specified level with the duty ratio retained.
Rev. 3.00 Jul. 14, 2005 Page 490 of 986
REJ09B0098-0300
Specified pulse width

Figure 15.31 Clock Output Fixing Timing

Specified pulse width