Pwm Data Registers 15 To 8 (Pwdr15 To Pwdr8); Table 9.2 Internal Clock Selection; Table 9.3 Resolution, Pwm Conversion Period, And Carrier Frequency When Φ = 20 Mhz - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Internal Clock Selection

Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz

Internal Clock

PWM Data Registers 15 to 8 (PWDR15 to PWDR8)

PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each

PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional

pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper

four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The

lower four bits specify how many extra pulses are to be added within the conversion period

comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios

within the conversion period. For 256/256 (100%) output, port output should be used.

Section 9 8-Bit PWM Timer (PWM)

Clock input is disabled

φ (system clock) is selected

φ/2 is selected

φ/4 is selected

φ/8 is selected

φ/16 is selected

PWM Conversion

Rev. 3.00 Jul. 14, 2005 Page 251 of 986

(Initial value)

Carrier Frequency

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r