Section 18 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
1
SMIE4
0
0
0
Rev. 3.00 Jul. 14, 2005 Page 652 of 986
REJ09B0098-0300
R/W
R/W
Host SMI Interrupt Enable 4
Enables or disables an SMI interrupt request when
OBF4 is set by an ODR4 write.
0: Host SMI interrupt request by OBF4 and SMIE4
is disabled
[Clearing conditions]
•
Writing 0 to SMIE4
•
LPC hardware reset, LPC software reset
•
Clearing OBF4 to 0 (when IEDIR4 = 0)
1: [When IEDIR4 = 0]
Host SMI interrupt request by setting OBF4 to 1 is
enabled
[When IEDIR4 = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE4 = 0
R/W
Reserved
The initial value should not be changed.