Table 16.10 Permissible Scl Rise Time - Renesas H8S Series Hardware Manual

4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
2
5. The I C bus interface specification for the SCL rise time t
high-speed mode). In master mode, the I
synchronizes one bit at a time during communication. If t
V ) exceeds the time determined by the input clock of the I
IH
SCL is extended. The SCL rise time is determined by the pull-up resistance and load
capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the
pull-up resistance and load capacitance so that the SCL rise time does not exceed the values
given in table 16.10.
Table 16.10 Permissible SCL Rise Time (t
IICX t Indication
cyc
0 7.5 t Standard mode
cyc
High-speed mode 300
1 17.5 t Standard mode
cyc
High-speed mode 300
2
6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
table 16.9. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t fails to meet the I
BUFO
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
2
C bus interface AC timing specifications will not be met with a
2
I C Bus
Specification
(Max.)
1000
1000
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
in standard mode fail to satisfy the I
STASO
, as shown in section 26, Electrical
cyc
is 1000 ns or less (300 ns for
sr
2
C bus interface monitors the SCL line and
(the time for SCL to go from low to
sr
2
C bus interface, the high period of
) Values
sr
Time Indication [ns]
φ = φ =
5 MHz 8 MHz
1000 937
300 300
1000 1000
300 300
2
C bus interface specifications may
/t . Possible solutions that should be
Sr Sf
Rev. 3.00 Jul. 14, 2005 Page 571 of 986
2
Section 16 I C Bus Interface (IIC)
φ = φ =
10 MHz 16 MHz
750 468
300 300
1000 1000
300 300
, as shown in
cyc
2
C bus.
2
C bus interface
REJ09B0098-0300
φ =
20 MHz
375
300
875
300
2
C