Figure 5.4 Block Diagram Of Interrupts Irq15 To Irq0 - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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Section 5 Interrupt Controller
IRQn
ISSm
ExIRQn
n = 15 to 0
m = 15 to 7 and 5 to 0
Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit in SYSCR3.

Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0

(3)
KIN15 to KIN0 Interrupts and WUE15 to WUE0 Interrupts
Interrupts KIN15 to KIN0 and WUE15 to WUE0 are requested by an input signal at pins KIN15
to KIN0 and WUE15 to WUE0. Interrupts KIN15 to KIN0 and WUE15 to WUE0 have the
following features according to the setting of the EIVS bit in system control register 3 (SYSCR3).
• H8S/2140B Group compatible vector mode (EIVS = 0 in SYSCR3)
 Interrupts WUE7 to WUE0 and KIN15 to KIN8 correspond to interrupt IRQ7, and
interrupts KIN7 to KIN0 correspond to interrupt IRQ6. The pin conditions for generating
an interrupt request, whether the interrupt request is enabled, interrupt control level setting,
and status of the interrupt request for the above interrupts are in accordance with the
settings and status of the relevant interrupts IRQ7 and IRQ6. Interrupt settings for
interrupts WUE15 to WUE8 can be made regardless of the settings for interrupts IRQ7 and
IRQ6.
 Enabling or disabling of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 can be
selected using KMIMRA, KMIMR, WUEMRB, and WUEMR.
 If the KIN7 to KIN0 pins or WUE15 to WUE8 pins, and WUE7 to WUE0 pins are
specified to be used as key-sensing interrupt input pins and wake-up event interrupt input
pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7)
must be set to low-level sensing or falling-edge sensing.
 When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared
to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8
and WUEMR7 to WUEMR0 bits must all be set to 1. If even one of these bits is cleared to
0, the IRQ7 interrupt input from the IRQ7 pin is ignored.
Rev. 3.00 Jul. 14, 2005 Page 100 of 986
REJ09B0098-0300
IRQnSCA, IRQnSCB
Edge/level
detection circuit
Clear signal
IRQnE
IRQnF
S
Q
R
IRQn interrupt
request

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