Figure 16.27 Iric Setting Timing And Scl Control (3) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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2
Section 16 I
C Bus Interface (IIC)
When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.

Figure 16.27 IRIC Setting Timing and SCL Control (3)

Rev. 3.00 Jul. 14, 2005 Page 564 of 986
REJ09B0098-0300
8
1
8
1
Clear IRIC
8
8
Clear IRIC
2
3
2
3
Write to ICDR (transmit)
or read from ICDR (receive)
4
4
1
1
Clear IRIC

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