Renesas H8S Series Hardware Manual page 113

Bit Bit Name Initial Value
3 FLSHE 0
2 — 0
1 ICKS1 0
0 ICKS0 0
R/W Description
R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS, and
FTDAR), power-down state control registers (SBYCR,
LPWRCR, MSTPCRH, and MSTPCRL), and on-chip
peripheral module control registers (BCR2, WSCR,
PCSR, and SYSCR2).
0: Control registers of power-down state and
peripheral modules are accessed in an area from
H'(FF)FF80 to H'(FF)FF87. Area from H'(FF)FEA8
to H'(FF)FEAE is reserved.
1: Control registers of flash memory are accessed in
an area from H'(FF)FEA8 to H'(FF)FEAE. Area from
H'(FF)FF80 to H'(FF)FF87 is reserved.
R/(W) Reserved
The initial value should not be changed.
R/W Internal Clock Source Select 1, 0
R/W
These bits select a clock to be input to the timer counter
(TCNT) and a count condition together with bits CKS2 to
CKS0 in the timer control register (TCR). For details, see
section 13.3.4, Timer Control Register (TCR).
Section 3 MCU Operating Modes
Rev. 3.00 Jul. 14, 2005 Page 65 of 986
REJ09B0098-0300