Renesas H8S/2368 Series Manuals

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Renesas H8S/2368 Series Hardware Manual (875 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 5.48 MB

General Precautions on Handling of Product
5
Preface
7
List of Registers
8
Register Bits
16
Table of Contents
21
Section 1 Overview
53
Features
53
Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363
55
Block Diagram
55
Figure
55
Figure 1.2 Internal Block Diagram of H8S/2366
56
Pin Description
57
Section 2 CPU
73
Features
73
CPU Operating Modes
76
Figure 2.5 Memory Map
80
Address Space
80
- Figure 2.6 CPU Internal Registers
  81
- Figure 2.7 Usage of General Registers
  82
- General Registers
  82
- Extended Control Register (EXR)
  83
- Program Counter (PC)
  83
- Stack
  83
- Condition-Code Register (CCR)
  84
- Initial Register Values
  86
Register Configuration
81
Data Formats
86
Instruction Set
89
Figure 2.11 Instruction Formats (Examples)
100
Addressing Modes and Effective Address Calculation
100
Processing States
106
Usage Note
107
- Note on Bit Manipulation Instructions
  107
- Figure 2.13 State Transitions
  107
Section 3 MCU Operating Modes
109
Operating Mode Selection
109
Register Descriptions
110
- Mode Control Register (MDCR)
  110
- System Control Register (SYSCR)
  110
Operating Mode Descriptions
112
- Mode 1
  112
- Mode 2
  112
- Mode 3
  112
- Mode 4
  112
- Mode 7
  113
- Pin Functions
  113
- Table 3.2 Pin Functions in each Operating Mode
  113
Memory Map in each Operating Mode
114
Figure 3.1 H8S/2367 Memory Map (1)
114
Figure 3.2 H8S/2367 Memory Map (2)
115
Figure 3.3 H8S/2366 Memory Map (1)
116
Figure 3.4 H8S/2366 Memory Map (2)
117
Figure 3.5 H8S/2365 Memory Map (1)
118
Figure 3.6 H8S/2365 Memory Map (2)
119
Figure 3.7 H8S/2363 Memory Map
120
Section 4 Exception Handling
121
Table 4.1 Exception Types and Priority
121
Exception Handling Types and Priority
121
Exception Sources and Exception Vector Table
121
Table 4.2 Exception Handling Vector Table
122
Reset
123
Table 4.3 Status of CCR and EXR after Trace Exception Handling
126
Traces
126
Interrupts
126
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
127
Trap Instruction
127
Stack Status after Exception Handling
128
Figure 4.3 Stack Status after Exception Handling
128
Usage Notes
129
Figure 4.4 Operation When SP Value Is Odd
129
Section 5 Interrupt Controller
131
Features
131
Input/Output Pins
133
Register Descriptions
133
Interrupt Sources
142
- External Interrupts
  142
- Internal Interrupts
  143
- Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
  143
Interrupt Exception Handling Vector Table
144
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
145
Interrupt Control Modes and Interrupt Operation
149
Usage Notes
155
Section 6 Bus Controller (BSC)
159
Features
159
Figure 6.1 Block Diagram of Bus Controller
160
Input/Output Pins
161
Table 6.1 Pin Configuration
161
Register Descriptions
162
Operation
184
- Area Division
  184
- Figure 6.5 Area Divisions
  185
- Bus Specifications
  186
- Table 6.2 Bus Specifications for each Area (Basic Bus Interface)
  187
- Memory Interfaces
  188
- Chip Select Signals
  189
- Figure 6.6 Csn Signal Output Timing (N = 0 to 7)
  189
Basic Bus Interface
190
DRAM Interface
204
Burst ROM Interface
228
Idle Cycle
231
Write Data Buffer Function
241
Table 6.8 Pin States in Idle Cycle
241
Bus Release
242
Bus Arbitration
246
- Operation
  246
- Bus Transfer Timing
  247
Bus Controller Operation in Reset
248
Usage Notes
248
Section 7 DMA Controller (DMAC)
251
Features
251
Figure 7.1 Block Diagram of DMAC
252
Register Descriptions
253
Input/Output Pins
253
Activation Sources
278
Operation
280
Table 7.12 Interrupt Sources and Priority Order
320
Figure 7.37 Example of Procedure for Clearing Full Address Mode
320
Interrupt Sources
320
Usage Notes
321
Section 8 Data Transfer Controller (DTC)
327
Features
327
Register Descriptions
328
Activation Sources
332
Location of Register Information and DTC Vector Table
333
Table 8.1 Relationship between Activation Sources and DTCER Clearing
333
Figure 8.2 Block Diagram of DTC Activation Source Control
333
Figure 8.3 Correspondence between DTC Vector Address and Register Information
334
Figure 8.4 Correspondence between DTC Vector Address and Register Information
334
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
335
Operation
336
Procedures for Using DTC
345
- Activation by Interrupt
  345
- Activation by Software
  345
Examples of Use of the DTC
345
- Normal Mode
  345
- Chain Transfer
  346
- Chain Transfer When Counter = 0
  347
- Software Activation
  348
- Figure 8.13 Chain Transfer When Counter = 0
  348
Usage Notes
349
- Module Stop Mode Setting
  349
- On-Chip RAM
  349
- DTCE Bit Setting
  349
- DMAC Transfer End Interrupt
  349
- Chain Transfer
  349
Section 9 I/O Ports
351
Table 9.1 Port Functions
352
Port 1
355
- Port 1 Data Direction Register (P1DDR)
  355
- Port 1 Data Register (P1DR)
  356
- Port 1 Register (PORT1)
  356
- Pin Functions
  357
Port 2
365
- Port 2 Data Direction Register (P2DDR)
  365
- Port 2 Data Register (P2DR)
  365
- Port 2 Register (PORT2)
  366
- Pin Functions
  367
Port 3
375
- Port 3 Data Direction Register (P3DDR)
  375
- Port 3 Data Register (P3DR)
  376
- Port 3 Register (PORT3)
  376
- Port 3 Open Drain Control Register (P3ODR)
  377
- Port Function Control Register 2 (PFCR2)
  378
- Pin Functions
  379
Port 4
382
- Port 4 Register (PORT4)
  382
- Pin Functions
  383
Port 5
385
- Port 5 Data Direction Register (P5DDR)
  385
- Port 5 Data Register (P5DR)
  385
- Port 5 Register (PORT5)
  386
- Pin Functions
  386
Port 8
388
- Port 8 Data Direction Register (P8DDR)
  388
- Port 8 Data Register (P8DR)
  389
- Port 8 Register (PORT8)
  389
- Pin Functions
  390
Port 9
391
- Port 9 Register (PORT9)
  391
- Pin Functions
  391
Port a
392
Port B
400
- Port B Data Direction Register (PBDDR)
  400
- Port B Data Register (PBDR)
  401
- Port B Register (PORTB)
  401
- Port B MOS Pull-Up Control Register (PBPCR)
  402
- Pin Functions
  402
- Port B MOS Input Pull-Up States
  403
- Table 9.3 MOS Input Pull-Up States (Port B)
  403
Port C
404
- Port C Data Direction Register (PCDDR)
  404
- Port C Data Register (PCDR)
  405
- Port C Register (PORTC)
  405
- Port C MOS Pull-Up Control Register (PCPCR)
  406
- Pin Functions
  406
- Port C MOS Input Pull-Up States
  407
- Table 9.4 MOS Input Pull-Up States (Port C)
  407
Port D
408
- Port D Data Direction Register (PDDDR)
  408
- Port D Data Register (PDDR)
  408
- Port D Register (PORTD)
  409
- Port D Pull-Up Control Register (PDPCR)
  409
- Pin Functions
  410
- Port D MOS Input Pull-Up States
  410
- Table 9.5 MOS Input Pull-Up States (Port D)
  410
Port E
411
- Port E Data Direction Register (PEDDR)
  411
- Port E Data Register (PEDR)
  412
- Port E Register (PORTE)
  412
- Port E Pull-Up Control Register (PEPCR)
  413
- Pin Functions
  413
- Port E MOS Input Pull-Up States
  414
Port F
414
- Table 9.6 MOS Input Pull-Up States (Port E)
  414
- Port F Data Direction Register (PFDDR)
  415
- Port F Data Register (PFDR)
  416
- Port F Register (PORTF)
  416
- Pin Functions
  417
Port G
420
- Port G Data Direction Register
  420
- Port G Data Register
  422
- Port G Register (PORTG)
  422
- Pin Functions
  423
Section 10 16-Bit Timer Pulse Unit (TPU)
425
Features
425
Table 10.1 TPU Functions
426
Figure 10.1 Block Diagram of TPU
428
Table 10.2 Pin Configuration
429
Input/Output Pins
429
Register Descriptions
430
- Timer Control Register (TCR)
  432
- Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)
  433
- Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
  433
- Table 10.5 TPSC2 to TPSC0 (Channel 0)
  434
- Table 10.6 TPSC2 to TPSC0 (Channel 1)
  434
- Table 10.7 TPSC2 to TPSC0 (Channel 2)
  435
- Table 10.8 TPSC2 to TPSC0 (Channel 3)
  435
- Table 10.9 TPSC2 to TPSC0 (Channel 4)
  436
- Table 10.10 TPSC2 to TPSC0 (Channel 5)
  436
- Timer Mode Register (TMDR)
  437
- Timer I/O Control Register (TIOR)
  438
- Table 10.11 MD3 to MD0
  438
- Table 10.12 TIORH_0
  440
- Table 10.13 TIORL_0
  441
- Table 10.14 TIOR_1
  442
- Table 10.15 TIOR_2
  443
- Table 10.16 TIORH_3
  444
- Table 10.17 TIORL_3
  445
- Table 10.18 TIOR_4
  446
- Table 10.19 TIOR_5
  447
- Table 10.20 TIORH_0
  448
- Table 10.21 TIORL_0
  449
- Table 10.22 TIOR_1
  450
- Table 10.23 TIOR_2
  451
- Table 10.24 TIORH_3
  452
- Table 10.25 TIORL_3
  453
- Table 10.26 TIOR_4
  454
- Table 10.27 TIOR_5
  455
- Timer Interrupt Enable Register (TIER)
  456
- Timer Status Register (TSR)
  458
- Timer Counter (TCNT)
  460
- Timer General Register (TGR)
  461
- Timer Start Register (TSTR)
  461
- Timer Synchronous Register (TSYR)
  462
Operation
463
Interrupts
487
Table 10.36 TPU Interrupts
488
DTC Activation
489
DMAC Activation
489
A/D Converter Activation
489
Operation Timing
490
Usage Notes
496
Section 11 Programmable Pulse Generator (PPG)
505
Features
505
Input/Output Pins
507
Register Descriptions
507
Operation
515
Usage Notes
524
Section 12 8-Bit Timers (TMR)
525
Features
525
Figure 12.1 Block Diagram of 8-Bit Timer Module
526
Input/Output Pins
527
Register Descriptions
527
- Timer Counter (TCNT)
  527
- Table 12.1 Pin Configuration
  527
- Time Constant Register a (TCORA)
  528
- Time Constant Register B (TCORB)
  528
- Timer Control Register (TCR)
  528
- Timer Control/Status Register (TCSR)
  530
- Table 12.2 Clock Input to TCNT and Count Condition
  530
Operation
533
- Pulse Output
  533
Operation Timing
534
Operation with Cascaded Connection
537
Interrupts
538
Usage Notes
540
Section 13 Watchdog Timer
547
Features
547
Input/Output Pin
548
Table 13.1 Pin Configuration
548
Figure 13.1 Block Diagram of WDT
548
Register Descriptions
549
Operation
552
- Watchdog Timer Mode
  552
- Interval Timer Mode
  553
- Figure 13.2 Operation in Watchdog Timer Mode
  553
Interrupts
554
Usage Notes
554
Section 14 Serial Communication Interface (SCI, Irda)
559
Features
559
Figure 14.1 Block Diagram of SCI
560
Input/Output Pins
561
Table 14.1 Pin Configuration
561
Register Descriptions
562
Operation in Asynchronous Mode
592
Multiprocessor Communication Function
603
Operation in Clocked Synchronous Mode
610
Operation in Smart Card Interface Mode
619
Figure 14.33 Block Diagram of Irda
629
Irda Operation
629
Figure 14.34 Irda Transmit/Receive Operations
630
Table 14.12 Settings of Bits Ircks2 to Ircks0
631
SCI Interrupts
632
Usage Notes
635
Section 15 I C Bus Interface2 (IIC2) (Option)
641
Features
641
Figure 15.1 Block Diagram of I
642
Table 15.1 Pin Configuration
643
Figure 15.2 External Circuit Connections of I/O Pins
643
Input/Output Pins
643
Register Descriptions
644
- C Bus Control Register a (ICCRA)
  645
- C Bus Control Register B (ICCRB)
  646
- Table 15.2 Transfer Rate
  646
- C Bus Mode Register (ICMR)
  648
- C Bus Interrupt Enable Register (ICIER)
  649
- C Bus Status Register (ICSR)
  651
- Slave Address Register (SAR)
  653
- C Bus Transmit Data Register (ICDRT)
  653
- C Bus Receive Data Register (ICDRR)
  653
- C Bus Shift Register (ICDRS)
  653
Operation
654
Table 15.3 Interrupt Requests
668
Interrupt Request
668
Bit Synchronous Circuit
668
Figure 15.18 Timing of the Bit Synchronous Circuit
668
Table 15.4 Time for Monitoring SCL
669
Section 16 A/D Converter
671
Features
671
Figure 16.1 Block Diagram of A/D Converter
672
Table 16.1 Pin Configuration
673
Input/Output Pins
673
Register Descriptions
674
Operation
678
- Single Mode
  678
- Scan Mode
  678
- Input Sampling and A/D Conversion Time
  679
- Figure 16.2 A/D Conversion Timing
  679
- Table 16.3 A/D Conversion Time (Single Mode)
  680
- Table 16.4 A/D Conversion Time (Scan Mode)
  680
- External Trigger Input Timing
  681
Table 16.5 A/D Converter Interrupt Source
681
Interrupts
681
Figure 16.3 External Trigger Input Timing
681
A/D Conversion Precision Definitions
682
Figure 16.4 A/D Conversion Precision Definitions
683
Figure 16.5 A/D Conversion Precision Definitions
683
Usage Notes
684
Section 17 D/A Converter
689
Features
689
Figure 17.1 Block Diagram of D/A Converter
690
Input/Output Pins
691
Register Descriptions
691
Operation
693
Usage Notes
694
Section 18 RAM
695
Section 19 Flash Memory (F-ZTAT Version)
697
Features
697
Figure 19.1 Block Diagram of Flash Memory
698
Mode Transitions
698
Figure 19.2 Flash Memory State Transitions
699
Table 19.1 Differences between Boot Mode and User Program Mode
699
Figure 19.3 Boot Mode
700
Figure 19.4 User Program Mode
701
Block Configuration
702
Figure 19.5 384-Kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)
703
Input/Output Pins
704
Register Descriptions
704
- Flash Memory Control Register 1 (FLMCR1)
  704
- Table 19.2 Pin Configuration
  704
- Flash Memory Control Register 2 (FLMCR2)
  706
- Erase Block Register 1 (EBR1)
  706
- Erase Block Register 2 (EBR2)
  707
- RAM Emulation Register (RAMER)
  708
- Table 19.3 Erase Blocks
  708
On-Board Programming Modes
709
Figure 19.7 Flowchart for Flash Memory Emulation in RAM
714
Flash Memory Emulation in RAM
714
Figure 19.8 Example of RAM Overlap Operation
715
Flash Memory Programming/Erasing
716
Program/Erase Protection
720
- Hardware Protection
  720
- Software Protection
  720
- Error Protection
  720
Table 19.7 Flash Memory Operating States
721
Programmer Mode
721
Power-Down States for Flash Memory
721
Usage Notes
721
Figure 19.11 Power-On/Off Timing
723
Figure 19.12 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode)
724
Figure 20.1 Block Diagram of 256-Kbyte Mask ROM (HD6432365)
725
Section 20 Mask ROM
725
Section 21 Clock Pulse Generator
727
Register Descriptions
727
Oscillator
730
Figure 21.5 External Clock Input Timing
732
Table 21.3 External Clock Input Conditions
732
PLL Circuit
732
Usage Notes
733
Frequency Divider
733
Section 22 Power-Down Modes
735
Table 22.1 Operating Modes and Internal States of the LSI
736
Figure 22.1 Mode Transitions
737
Register Descriptions
738
Operation
742
- Clock Division Mode
  742
- Sleep Mode
  742
- Software Standby Mode
  743
- Table 22.2 Oscillation Stabilization Time Settings
  744
- Hardware Standby Mode
  745
- Figure 22.2 Software Standby Mode Application Example
  745
- Module Stop Mode
  746
- Figure 22.3 Hardware Standby Mode Timing
  746
- All-Module-Clocks-Stop Mode
  747
Clock Output Control
747
Table 22.3 Φ Pin State in each Processing State
747
Usage Notes
748
Section 23 List of Registers
751
Register Addresses (Address Order)
752
Register Bits
762
Register States in each Operating Mode
775
Section 24 Electrical Characteristics
785
Electrical Characteristics of Masked ROM and Romless Versions
785
Electrical Characteristics of F-ZTAT Version
821
- Absolute Maximum Ratings
  821
- Table 24.13 Absolute Maximum Ratings
  821
- DC Characteristics
  822
- Table 24.14 DC Characteristics (1)
  822
- Table 24.15 DC Characteristics (2)
  823
- Table 24.16 Permissible Output Currents
  824
- Table 24.17 Clock Timing
  825
- Table 24.18 Control Signal Timing
  826
- Table 24.19 Bus Timing (1)
  827
- Table 24.20 Bus Timing (2)
  828
- Table 24.21 DMAC Timing
  829
- Table 24.22 Timing of On-Chip Peripheral Modules
  830
- A/D Conversion Characteristics
  832
- D/A Conversion Characteristics
  832
- Table 24.23 A/D Conversion Characteristics
  832
- Table 24.24 D/A Conversion Characteristics
  832
Flash Memory Characteristics
833
Table 24.25 Flash Memory Characteristics
833
Usage Note
835
Appendix
837
I/O Port States in each Pin State
837
Product Lineup
844
Package Dimensions
845
Figure C.1 Package Dimensions (TFP-120)
845
Figure C.2 Package Dimensions (FP-128B)
846
Bus State During Execution of Instructions
847
Figure D.1 Timing of Address Bus, RD, HWR, and LWR (8-Bit Bus, 3-State Access, no Wait)
848
Table D.1 Execution State of Instructions
849
Index
869
Section 14 Serial Communication Interface (SCI, Irda)
872
Section 13 Watchdog Timer
872

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