Ddc Switch Register (Ddcswr) - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)
16.3.7

DDC Switch Register (DDCSWR)

DDCSWR controls IIC internal latch clearance.
Bit Bit Name Initial Value R/W Description
7 to 5 — All 0
4 — 0
3 CLR3 1
2 CLR2 1
1 CLR1 1
0 CLR0 1
Note: * This bit is always read as 1.
Rev. 3.00 Jul. 14, 2005 Page 530 of 986
REJ09B0098-0300
R/W Reserved
The initial value should not be changed.
R Reserved
W* IIC Clear 3 to 0
W* Controls initialization of the internal state of IIC_0 and
IIC_1.
W*
00--: Setting prohibited
W*
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a clear
signal is generated for the internal latch circuit of the
corresponding module, and the internal state of the IIC
module is initialized.
These bits can only be written to; they are always read as
1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not
use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be written
to in accordance with the setting.