Figure 2.13 State Transitions - Renesas H8S Series Hardware Manual

End of bus
request
Bus-released state
End of
exception
handling
Exception-handling state
RES = high
*1
Reset state
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
Notes: 1.
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
2.
3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 24, Power-Down Modes.
End of bus request
Bus request
Program execution
state
SLEEP
Bus
instruction
request
with
LSON = 0,
PSS = 0,
SSBY = 1
Request for
exception
handling
Interrupt
request
External interrupt
request
STBY = high, RES = low

Figure 2.13 State Transitions

SLEEP
instruction
with
LSON = 0,
SSBY = 0
Sleep mode
Software standby mode
*2
Hardware standby mode
*3
Power-down state
Rev. 3.00 Jul. 14, 2005 Page 55 of 986
REJ09B0098-0300
Section 2 CPU