Figure 16.8 Example Of Operation Timing In Master Transmit Mode (Mls = Wait = 0) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output) [5]
ICDRE
IRIC
Interrupt
request
IRTR
ICDRT
ICDRS
Note:* Data write
in ICDR
prohibited
[4] BBSY set to 1
User processing
SCP cleared to 0
(start condition issuance)

Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)

Rev. 3.00 Jul. 14, 2005 Page 540 of 986
REJ09B0098-0300
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Slave address
Address + R/W
Address + R/W
[6] ICDR write
[6] IRIC clear
5 6 7 8 9
Bit 3 Bit 2 Bit 1 Bit 0
R/W [7]
A
Interrupt
request
[9] ICDR write
1 2
Bit 7 Bit 6
Data 1
Data 1
Data 1
[9] IRIC clear