Section 6 Bus Controller (Bsc); Features; Figure 6.1 Block Diagram Of Bsc - Renesas H8S Series Hardware Manual

This LSI has an on-chip bus controller (BSC).
The BSC has a bus arbitration function, and controls the operation of the internal bus masters –
CPU, data transfer controller (DTC), and LPC interface (LPC).
Though this LSI does not have external extended functions, take care not to set inappropriate
values in the control registers related to the bus controller when utilizing software with other
similar products.
6.1

Features

• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and LPC.
BSCS20AA_000020020700

Section 6 Bus Controller (BSC)

Bus controller
BCR
WSCR
Bus arbiter

Figure 6.1 Block Diagram of BSC

Section 6 Bus Controller (BSC)
Internal control signals
Bus mode signal
CPU bus request signal
DTC bus request signal
LPC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
LPC bus acknowledge signal
Rev. 3.00 Jul. 14, 2005 Page 129 of 986
REJ09B0098-0300