Figure 16.1 Block Diagram Of I - Renesas H8S Series Hardware Manual

Figure 16.1 shows a block diagram of the I
pin connections to external circuits. Since I
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 26, Electrical Characteristics.
φ
*
SCL
ExSCLA
ExSCLB
*
SDA
ExSDAA
ExSDAB
Note : * An input/output pin can be
[Legend]
2
ICCR: I C bus control register
2
ICMR: I C bus mode register
2
ICSR: I C bus status register
2
ICDR: I C bus data register
2
ICXR: I C bus extended control register
SAR: Slave address register
SARX: Slave address register X
PS: Prescaler
PS
Clock
control
Noise
canceler
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Noise
canceler
selected among three pins.

Figure 16.1 Block Diagram of I

2
C bus interface. Figure 16.2 shows an example of I/O
2
C bus interface I/O pins are different in structure from
2
C Bus Interface
Rev. 3.00 Jul. 14, 2005 Page 507 of 986
2
Section 16 I C Bus Interface (IIC)
ICXR
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address
comparator
SAR, SARX
Interrupt
Interrupt
generator
request
REJ09B0098-0300