Input Data Registers 1 To 4 (Idr1 To Idr4) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
• Host select register
Bits 5 to 3
Bits 15 to 3 in LADR4
Bits 15 to 3 in LADR4
Bits 15 to 3 in LADR4
Bits 15 to 3 in LADR4
Note: When channel 4 is used, the content of LADR4 must be set so that the addresses for
*
channels 1, 2, and 3 are different.
18.3.6

Input Data Registers 1 to 4 (IDR1 to IDR4)

IDR1 to IDR4 are 8-bit read-only registers for the slave (this LSI), and 8-bit write-only registers
for the host. The registers selected from the host according to the I/O address are shown in the
following table. For information on IDR3 and IDR4 selection, see the section of the corresponding
LADR. Data transferred in an LPC I/O write cycle is written to the selected register. The value of
bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written
information is a command or data. The initial values of IDR1 to IDR4 are undefined.
Bits 15 to 4 Bit 3
Bits 15 to 4 Bit 3
Bits 15 to 4 Bit 3
n = 1 to 4
Note: In bits 15 to 0, channel 1 corresponds to H'0060/H'0064, channel 2 corresponds to
H'0062/H'0066.
Rev. 3.00 Jul. 14, 2005 Page 632 of 986
REJ09B0098-0300
I/O Address
Bit 2 Bits 1 and 0
0 Bits 1 and 0 in LADR4
1 Bits 1 and 0 in LADR4
0 Bits 1 and 0 in LADR4
1 Bits 1 and 0 in LADR4
I/O Address
Bit 2 Bit 1
0 Bit 1
1 Bit 1
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
Transfer
Cycle
Bit 0
Bit 0 I/O write
Bit 0 I/O write
Host Select Register
IDR4 write (data)
IDR4 write (command)
ODR4 read
STR4 read
Host Register Selection
IDRn write, C/Dn ← 0
IDRn write, C/Dn ← 1