Renesas H8S Series Hardware Manual page 822

Section 21 Flash Memory (0.18-µm F-ZTAT Version)
CPU should be set to B'11 in interrupt control mode 1. This enables interrupts other than NMI to
be held and not executed.
The NMI interrupt must be masked within the user system.
The interrupts that are held must be executed after all programming processings.
When a bus master other than the CPU, such as the DTC or LPC, acquires the bus, the error-
protection state is entered. Therefore, the DTC or LPC acquiring the bus must also be prohibited.
(j) Set H'5A in FKEY and prepare the user MAT for programming.
(k) Set the parameters required for programming.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1, and the start address of the program data area (FMPDR) is set to general register
ER0.
• Example of FMPAR setting
FMPAR specifies the programming destination address. When an address other than one in the
user MAT area is specified, even if the programming program is executed, programming is not
executed and an error is returned to the return value parameter FPFR. Since the programming
unit is 128 bytes, the lower eight bits of the address must be at the 128-byte boundary of H'00
or H'80.
• Example of FMPDR setting
When the storage destination of the program data is flash memory, even if the programming
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM before
programming is executed.
Rev. 3.00 Jul. 14, 2005 Page 774 of 986
REJ09B0098-0300