12.8.11 Conflict Between Tcnt Write And Overflow/Underflow; 12.8.12 Multiplexing Of I/O Pins; 12.8.13 Module Stop Mode Setting; Figure 12.53 Conflict Between Tcnt Write And Overflow - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)

12.8.11 Conflict between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set. Figure 12.53 shows the operation timing when there is conflict between TCNT write and
overflow.
φ
Address
Write signal
TCNT
TCFV flag

Figure 12.53 Conflict between TCNT Write and Overflow

12.8.12 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.

12.8.13 Module Stop Mode Setting

TPU operation can be enabled or disabled by the module stop control register. In the initial state,
TPU operation is disabled. Access to TPU registers is enabled when module stop mode is
cancelled. For details, see section 24, Power-Down Modes.
Rev. 3.00 Jul. 14, 2005 Page 376 of 986
REJ09B0098-0300
state of a TCNT write cycle, and
2
TCNT write cycle
T1 T2
TCNT address
H'FFFF
TCNT write data
M