Peripheral Clock Select Register (Pcsr); Table 10.2 Clock Select Of Pwmx - Renesas H8S Series Hardware Manual

10.3.4

Peripheral Clock Select Register (PCSR)

PCSR and the CKS bit of DACR select the operating speed.
Bit Bit Name Initial Value

7 0

6 0
5 PWCKXB 0
4 PWCKXA 0

3 0
2 PWCKB 0
1 PWCKA 0
0 PWCKXC 0

Table 10.2 Clock Select of PWMX

PWCKXC PWCKXB
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
R/W Description
R/W Reserved
R/W The initial value should not be changed.
R/W PWMX clock select
R/W These bits select a clock cycle with the CKS bit of
DACR of PWMX being 1.
See table 10.2.
R/W Reserved
The initial value should not be changed.
R/W PWM clock select B, A
R/W See section 9.3.5, Peripheral Clock Select Register
(PCSR).
R/W PWMX clock select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX being 1.
See table 10.2.
PWCKXA Resolution (T)
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Operates on the system clock cycle (t
0 Operates on the system clock cycle (t
1 Setting prohibited
Section 10 14-Bit PWM Timer (PWMX)
Rev. 3.00 Jul. 14, 2005 Page 265 of 986
REJ09B0098-0300
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