Renesas H8S Series Hardware Manual page 694

Section 18 LPC Interface (LPC)
Bit Bit Name Initial Value Slave Host Description
4 IRQ6E3 0
3 IRQ11E2 0
Rev. 3.00 Jul. 14, 2005 Page 646 of 986
REJ09B0098-0300
R/W

R/W Host IRQ6 Interrupt Enable 3
Enables or disables an HIRQ6 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ6 interrupt request by OBF3A and IRQE6E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ6 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ6 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ6E3 = 0

R/W Host IRQ11 Interrupt Enable 2
Enables or disables an HIRQ11 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ11 interrupt request by OBF2 and
IRQE11E2 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ11 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ11E2 = 0