Register Descriptions; Instruction Register (Sdir); Table 22.2 Jtag Register Serial Transfer - Renesas H8S Series Hardware Manual

Section 22 Boundary Scan (JTAG)
22.3

Register Descriptions

The JTAG has the following registers.

• Instruction register (SDIR)

• Bypass register (SDBPR)
• Boundary scan register (SDBSR)
• ID code register (SDIDR)
Instructions can be input to the instruction register (SDIR) by serial transfer from the test data
input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass
register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS,
CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 334-bit register to which the
ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code
register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE
mode. All registers cannot be accessed directly by the CPU.
Table 22.2 shows the kinds of serial transfer possible with each JTAG register.

Table 22.2 JTAG Register Serial Transfer

Register
SDIR
SDBPR
SDBSR
SDIDR
22.3.1 Instruction Register (SDIR)
SDIR is a 32-bit read-only register. JTAG instructions can be transferred to SDIR by serial input
from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is
in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode.
Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the
last 4 bits of the serial data will be stored in SDIR.
Rev. 3.00 Jul. 14, 2005 Page 830 of 986
REJ09B0098-0300
Serial Input
Possible
Possible
Possible
Impossible
Serial Output
Possible
Possible
Possible
Possible