Timer Output Compare Control Register (Tocr) - Renesas H8S Series Hardware Manual

Bit Bit Name Initial Value
1 CKS1 0
0 CKS0 0
11.3.9

Timer Output Compare Control Register (TOCR)

TOCR enables output from the output compare pins, selects the output levels, switches access
between output compare registers A and B, controls the ICRD and OCRA operating modes, and
switches access to input capture registers A, B, and C.
Bit Bit Name Initial Value
7 ICRDMS 0
6 OCRAMS 0
5 ICRS 0
R/W Description
R/W Clock Select 1, 0
Select clock source for FRC.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: External clock source (counting at FTCI rising edge)
R/W Description
R/W Input Capture D Mode Select
Specifies whether ICRD is used in the normal operating
mode or in the operating mode using OCRDM.
0: The normal operating mode is specified for ICRD
1: The operating mode using OCRDM is specified for
ICRD
R/W Output Compare A Mode Select
Specifies whether OCRA is used in the normal
operating mode or in the operating mode using OCRAR
and OCRAF.
0: The normal operating mode is specified for OCRA
1: The operating mode using OCRAR and OCRAF is
specified for OCRA
R/W Input Capture Register Select
The same addresses are shared by ICRA and OCRAR,
by ICRB and OCRAF, and by ICRC and OCRDM. The
ICRS bit determines which registers are selected when
the shared addresses are read from or written to. The
operation of ICRA, ICRB, and ICRC is not affected.
0: ICRA, ICRB, and ICRC are selected
1: OCRAR, OCRAF, and OCRDM are selected
Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Jul. 14, 2005 Page 287 of 986
REJ09B0098-0300