Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.18 PWM Output Registers and Output Pins
Channel
0
1
2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
(1)
Example of PWM Mode Setting Procedure
Figure 12.21 shows an example of the PWM mode setting procedure.
Select counter clock
Select counter clearing source
Select waveform output level
Set PWM mode
<PWM mode>
Figure 12.21 Example of PWM Mode Setting Procedure
Rev. 3.00 Jul. 14, 2005 Page 348 of 986
REJ09B0098-0300
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
PWM mode
[1]
[2]
[3]
Set TGR
[4]
[5]
Start count
[6]
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
[1]
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
[2]
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
[3]
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4]
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5]
Select the PWM mode with bits MD3 to MD0 in
TMDR.
[6]
Set the CST bit in TSTR to 1 start the count
operation.
Output Pins
PWM Mode 2
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2