On-Chip Ram Address Translation (Host → Slave); Figure 18.10 Example Of On-Chip Ram Address Translation - Renesas H8S Series Hardware Manual

1. Host address − HBAR1 = H'000FFFF0 − H'000E0000 = H'0001FFF0
2. H'0001FFF0 + SAR1 = H'0001FFF0 + H'050000 = H'06FFF0 (slave address)
18.4.10 On-Chip RAM Address Translation (Host → Slave)
A host address is translated into an on-chip RAM address by the settings of RAMBAR, RAMSSR,
and RAMAR. The slave address which exceeds H'FFEFFF must not be specified. The host
addresses within the range of H'00000000 to H'FFFFFFFF are available for translation and the
on-chip RAM addresses within the range of H'FFD100 to H'FFEFFF are available. Figure 18.10
shows an example of the on-chip RAM address translation.
RAMBAR: H1'000
RAMASSR: H'FF (8 kbytes to 256 bytes)
RAMAR: H'D1
Host address: H'10000100
H'10000000
H'10001EFF

Figure 18.10 Example of On-Chip RAM Address Translation

The host address space is specified by the settings of RAMBAR and RAMASSR as shown in
figure 18.10. The host must use addresses within this range. An access to the addresses which are
not within this range will cause an address exception and any memory access is not performed.
The slave address space is specified by the settings of RAMAR and RAMASSR as shown in
figure 18.10.
The host address of H'10000100 is translated shown below.
1. Host address − RAMBAR = H'10000100 − H'10000000 = H'00000100
2. H'0000100 + RAMAR = H'00000100 + H'FFD100 = H'FFD200 (slave address)
8 kbytes
to 256 bytes
Host address
Section 18 LPC Interface (LPC)
H'FFD100
On-chip RAM
H'FFEFFF
Slave address
Rev. 3.00 Jul. 14, 2005 Page 701 of 986
REJ09B0098-0300