Table 12.11 Tiorl_0 (Channel 0) - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)

Table 12.11 TIORL_0 (channel 0)

Bit 7 Bit 6
IOD3 IOD2
0 0
1
1 0
1
[Legend]
×:
Don't care
Note: When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Jul. 14, 2005 Page 320 of 986
REJ09B0098-0300
Bit 5 Bit 4
IOD1 IOD0
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
×
1
× ×
TGRA_0
Function TIOCD0 Pin Function
Output Output disabled
Compare
Initial output is 0 output
register*
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Input capture Capture input source is TIOCD0 pin
register* Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
Capture input source is TIOCD0 pin
Input capture at both edges
Setting prohibited
Description