Input/Output Pins; Table 18.1 Pin Configuration - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
18.2

Input/Output Pins

Table 18.1 lists the LPC pin configuration.

Table 18.1 Pin Configuration

Name Abbreviation
LPC address/ LAD3 to LAD0 P33 to P30 I/O
data 3 to 0
LFRAME
LPC frame
LRESET
LPC reset
LPC clock LCLK
Serialized SERIRQ
interrupt request
LSCI general LSCI
output
LSMI
LSMI general
output
PME
PME general
output
GATE A20 GA20
CLKRUN
LPC clock run
LPC power-down LPCPD
Docking LPC DLAD3 to
address/ DLAD0
data 3 to 0
DLFRAME
Docking LPC
frame
Docking serialized DSERIRQ
interrupt request
DCLKRUN
Docking LPC
clock run
Rev. 3.00 Jul. 14, 2005 Page 616 of 986
REJ09B0098-0300
Port I/O
1
P34 Input*
1
P35 Input*
P36 Input
1
P37 I/O*
1,
PB1 Output*
1,
PB0 Output*
1,
P80 Output*
1,
P81 Output*
1, 2
P82 I/O*
*
1
P83 Input*
3
PB4 to PB7 I/O*
3
PB3 I/O*
3
P40 I/O*
3
P41 I/O*
Function
Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
Transfer cycle start and forced
termination signal
LPC interface reset signal
33-MHz PCI clock signal
Serialized host interrupt request
signal (SMI, HIRQ1, HIRQ6, HIRQ9
to HIRQ12) in synchronization with
LCLK
2
General output
*
2
General output
*
2
General output
*
2
* Gate A20 control signal output
LCLK restart request signal when
serial host interrupt is requested
LPC module shutdown signal
Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
Transfer cycle start and forced
termination signal
Serialized host interrupt request
signal in synchronization with LCLK
LCLK restart request signal when
serial host interrupt is requested