Figure 12.54 Contention Between Overflow And Counter Clearing; Figure 12.55 Contention Between Tcnt Write And Overflow - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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φ
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV

Figure 12.54 Contention between Overflow and Counter Clearing

Contention between TCNT Write and Overflow/Underflow:
If there is an up-count or down-count in the T2 state of a TCNT write cycle and
overflow/underflow occurs, the TCNT write takes priority and the TCFV/TCFU flag in TSR is not
set. Figure 12.55 shows the operation timing when there is contention between TCNT write and
overflow.
φ
Address
Write signal
TCNT
TCFV flag

Figure 12.55 Contention between TCNT Write and Overflow

Rev. 1.00, 09/03, page 362 of 704
H'FFFF
Disabled
TCNT write cycle
T
1
TCNT address
H'FFFF
H'0000
T
2
TCNT write data
M

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