Host Interface Control Register 4 (Hicr4) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
• HICR3
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined
6 CLKRUN Undefined
5 SERIRQ Undefined
4 LRESET Undefined
3 LPCPD Undefined
2 PME Undefined
1 LSMI Undefined
0 LSCI Undefined
18.3.3

Host Interface Control Register 4 (HICR4)

HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface
slave (this LSI).
Bit Bit Name Initial Value Slave Host Description

7 0
6 LPC4E 0
5 IBFIE4 0
4 to 0 
All 0
Rev. 3.00 Jul. 14, 2005 Page 628 of 986
REJ09B0098-0300
R/W
LFRAME Pin Monitor

R
CLKRUN Pin Monitor

R

R SERIRQ Pin Monitor
LRESET Pin Monitor

R
LPCPD Pin Monitor

R
PME Pin Monitor

R
LSMI Pin Monitor

R

R LSCI Pin Monitor
R/W

R/W Reserved
The initial value bit should not be changed.

R/W LPC Enable 4
0: LPC channel 4 is disabled
For IDR4, ODR4, and STR4, address (LADR4)
match is not occurred.
1: LPC channel 4 enabled

R/W IDR4 Receive Completion Enable
Enables or disables IBFI4 interrupt to the slave (this
LSI).
0: Input data register (IDR4) receive complete
interrupt requests disabled
1: Input data register (IDR4) receive complete
interrupt requests enabled

R/W Reserved
The initial value should not be changed.