Renesas H8S Series Hardware Manual page 31

Section 1 Overview
Figure 1.1 H8S/2114R Group Internal Block Diagram .................................................................. 3
Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)........................................................... 4
Figure 1.3 Sample Design of Reset Signals with no Affection Each Other.................................. 17
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 23
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 23
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 24
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 25
Figure 2.5 Memory Map............................................................................................................... 26
Figure 2.6 CPU Internal Registers ................................................................................................ 27
Figure 2.7 Usage of General Registers ......................................................................................... 28
Figure 2.8 Stack............................................................................................................................ 29
Figure 2.9 General Register Data Formats (1).............................................................................. 32
Figure 2.9 General Register Data Formats (2).............................................................................. 33
Figure 2.10 Memory Data Formats............................................................................................... 34
Figure 2.11 Instruction Formats (Examples) ................................................................................ 47
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 51
Figure 2.13 State Transitions ........................................................................................................ 55
Section 3 MCU Operating Modes
Figure 3.1 Address Map ............................................................................................................... 68
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 2)............................................................................................ 75
Figure 4.2 Stack Status after Exception Handling ........................................................................ 77
Figure 4.3 Operation when SP Value Is Odd................................................................................ 78
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 80
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,
WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB
(H8S/2140B Group Compatible Vector Mode: EIVS = 0).......................................... 95
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,
WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB
(Extended Vector Mode: EIVS = 1) ............................................................................ 96
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 ............................................................ 100
Figures
Rev. 3.00 Jul. 14, 2005 Page xxxi of xlviii